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Searched refs:eventsel (Results 1 – 16 of 16) sorted by relevance

/linux/arch/x86/kvm/
A Dpmu.c405 u64 eventsel) in is_gp_event_allowed() argument
453 u64 eventsel = pmc->eventsel; in reprogram_counter() local
454 u64 new_config = eventsel; in reprogram_counter()
473 eventsel |= ARCH_PERFMON_EVENTSEL_OS; in reprogram_counter()
475 eventsel |= ARCH_PERFMON_EVENTSEL_USR; in reprogram_counter()
477 eventsel |= ARCH_PERFMON_EVENTSEL_INT; in reprogram_counter()
489 (eventsel & pmu->raw_event_mask), in reprogram_counter()
492 eventsel & ARCH_PERFMON_EVENTSEL_INT); in reprogram_counter()
738 pmc->eventsel = 0; in kvm_pmu_reset()
843 config = pmc->eventsel; in cpl_is_matched()
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A Dpmu.h177 return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE; in pmc_speculative_in_use()
275 void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 eventsel);
/linux/tools/testing/selftests/kvm/include/x86_64/
A Dpmu.h18 #define RAW_EVENT(eventsel, umask) (((eventsel & 0xf00UL) << 24) | \ argument
19 ((eventsel) & 0xff) | \
/linux/arch/x86/kvm/vmx/
A Dpmu_intel.c330 msr_info->data = pmc->eventsel; in intel_pmu_get_msr()
402 if (data != pmc->eventsel) { in intel_pmu_set_msr()
403 pmc->eventsel = data; in intel_pmu_set_msr()
437 u64 eventsel; in intel_get_fixed_pmc_eventsel() local
446 eventsel = perf_get_hw_event_config(fixed_pmc_perf_ids[index]); in intel_get_fixed_pmc_eventsel()
447 WARN_ON_ONCE(!eventsel && index < kvm_pmu_cap.num_counters_fixed); in intel_get_fixed_pmc_eventsel()
448 return eventsel; in intel_get_fixed_pmc_eventsel()
585 pmu->fixed_counters[i].eventsel = intel_get_fixed_pmc_eventsel(i); in intel_pmu_init()
/linux/arch/x86/kvm/svm/
A Dpmu.c142 msr_info->data = pmc->eventsel; in amd_pmu_get_msr()
166 if (data != pmc->eventsel) { in amd_pmu_set_msr()
167 pmc->eventsel = data; in amd_pmu_set_msr()
/linux/arch/arm64/kvm/
A Dpmu-emul.c602 u64 eventsel, reg, data; in kvm_pmu_create_perf_event() local
610 eventsel = ARMV8_PMUV3_PERFCTR_CPU_CYCLES; in kvm_pmu_create_perf_event()
612 eventsel = data & kvm_pmu_event_mask(vcpu->kvm); in kvm_pmu_create_perf_event()
618 if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR || in kvm_pmu_create_perf_event()
619 eventsel == ARMV8_PMUV3_PERFCTR_CHAIN) in kvm_pmu_create_perf_event()
627 !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) in kvm_pmu_create_perf_event()
644 attr.config = eventsel; in kvm_pmu_create_perf_event()
/linux/arch/x86/events/amd/
A Dcore.c315 static inline int amd_pmu_addr_offset(int index, bool eventsel) in amd_pmu_addr_offset() argument
322 if (eventsel) in amd_pmu_addr_offset()
335 if (eventsel) in amd_pmu_addr_offset()
1313 .eventsel = MSR_K7_EVNTSEL0,
1415 x86_pmu.eventsel = MSR_F15H_PERF_CTL; in amd_core_pmu_init()
/linux/drivers/gpu/drm/amd/amdgpu/
A Ddf_v3_6.c412 uint32_t eventsel, instance, unitmask; in df_v3_6_pmc_get_ctrl_settings() local
424 eventsel = DF_V3_6_GET_EVENT(config) & 0x3f; in df_v3_6_pmc_get_ctrl_settings()
432 *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel; in df_v3_6_pmc_get_ctrl_settings()
/linux/arch/x86/events/intel/
A Dp6.c210 .eventsel = MSR_P6_EVNTSEL0,
A Dknc.c299 .eventsel = MSR_KNC_EVNTSEL0,
A Dp4.c1345 .eventsel = MSR_P4_BPU_CCCR0,
A Dcore.c5211 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
5265 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6235 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel) in intel_pmu_v6_addr_offset() argument
7222 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A; in intel_pmu_init()
/linux/tools/testing/selftests/kvm/x86_64/
A Dpmu_counters_test.c257 uint64_t eventsel = ARCH_PERFMON_EVENTSEL_OS | in guest_test_arch_event() local
266 MSR_P6_EVNTSEL0 + i, eventsel); in guest_test_arch_event()
/linux/arch/x86/events/
A Dperf_event.h788 unsigned eventsel; member
791 int (*addr_offset)(int index, bool eventsel);
1138 return x86_pmu.eventsel + (x86_pmu.addr_offset ? in x86_pmu_config_addr()
/linux/arch/x86/events/zhaoxin/
A Dcore.c468 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
/linux/arch/x86/include/asm/
A Dkvm_host.h522 u64 eventsel; member

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