Home
last modified time | relevance | path

Searched refs:fclk (Results 1 – 25 of 93) sorted by relevance

1234

/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/
A Ddml2_mcg_dcn4.c54 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clk_table_fine_grained()
59 min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[0]; in build_min_clk_table_fine_grained()
76 …am_bw_table.entries[i].min_fclk_khz, soc_bb->clk_table.fclk.clk_values_khz, soc_bb->clk_table.fclk… in build_min_clk_table_fine_grained()
108 min_table->dram_bw_table.entries[i].min_fclk_khz > min_table->max_clocks_khz.fclk) { in build_min_clk_table_fine_grained()
140 min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i]; in build_min_clk_table_coarse_grained()
155 if (soc_bb->clk_table.dcfclk.num_clk_values < 2 || soc_bb->clk_table.fclk.num_clk_values < 2) in build_min_clock_table()
165 if (soc_bb->clk_table.fclk.num_clk_values == 2) { in build_min_clock_table()
169 if (soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.dcfclk.num_clk_values && in build_min_clock_table()
170 soc_bb->clk_table.fclk.num_clk_values == soc_bb->clk_table.uclk.num_clk_values) in build_min_clock_table()
186 …min_table->max_clocks_khz.fclk = soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_… in build_min_clock_table()
/linux/drivers/usb/host/
A Dehci-sh.c13 struct clk *iclk, *fclk; member
114 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck"); in ehci_hcd_sh_probe()
115 if (IS_ERR(priv->fclk)) in ehci_hcd_sh_probe()
116 priv->fclk = NULL; in ehci_hcd_sh_probe()
122 clk_enable(priv->fclk); in ehci_hcd_sh_probe()
139 clk_disable(priv->fclk); in ehci_hcd_sh_probe()
157 clk_disable(priv->fclk); in ehci_hcd_sh_remove()
A Dohci-at91.c54 struct clk *fclk; member
78 clk_set_rate(ohci_at91->fclk, 48000000); in at91_start_clock()
81 clk_prepare_enable(ohci_at91->fclk); in at91_start_clock()
90 clk_disable_unprepare(ohci_at91->fclk); in at91_stop_clock()
215 ohci_at91->fclk = devm_clk_get(dev, "uhpck"); in usb_hcd_at91_probe()
216 if (IS_ERR(ohci_at91->fclk)) { in usb_hcd_at91_probe()
218 retval = PTR_ERR(ohci_at91->fclk); in usb_hcd_at91_probe()
/linux/Documentation/devicetree/bindings/clock/
A Damlogic,c3-peripherals-clkc.yaml29 - description: input fclk div 2
30 - description: input fclk div 2p5
31 - description: input fclk div 3
32 - description: input fclk div 4
33 - description: input fclk div 5
34 - description: input fclk div 7
/linux/Documentation/devicetree/bindings/display/ti/
A Dti,omap3-dss.txt14 - clocks: handle to fclk
37 - clocks: handle to fclk
52 - clocks: handles to fclk and iclk
64 - clocks: handle to fclk
82 - clocks: handles to fclk and pll clock
A Dti,omap4-dss.txt14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
67 - clocks: handle to fclk
88 - clocks: handles to fclk and pll clock
111 - clocks: handles to fclk and pll clock
A Dti,omap5-dss.txt14 - clocks: handle to fclk
36 - clocks: handle to fclk
51 - clocks: handles to fclk and iclk
69 - clocks: handles to fclk and pll clock
92 - clocks: handles to fclk and pll clock
A Dti,dra7-dss.txt14 - clocks: handle to fclk
47 - clocks: handle to fclk
66 - clocks: handles to fclk and pll clock
/linux/drivers/media/dvb-frontends/
A Ds5h1420.c39 u32 fclk; member
368 tmp = state->fclk / tmp; in s5h1420_read_status()
475 do_div(val, (state->fclk / 1000)); in s5h1420_setsymbolrate()
530 val = (((-val) * (state->fclk/1000000)) / (1<<24)); in s5h1420_getfreqoffset()
668 state->fclk = 80000000; in s5h1420_set_frontend()
670 state->fclk = 59000000; in s5h1420_set_frontend()
672 state->fclk = 86000000; in s5h1420_set_frontend()
674 state->fclk = 88000000; in s5h1420_set_frontend()
676 state->fclk = 44000000; in s5h1420_set_frontend()
678 …dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1)… in s5h1420_set_frontend()
[all …]
A Dcx24110.c231 u32 tmp, fclk, BDRI; in cx24110_set_symbolrate() local
251 fclk=90999000UL/2; in cx24110_set_symbolrate()
255 fclk=60666000UL; in cx24110_set_symbolrate()
259 fclk=80888000UL; in cx24110_set_symbolrate()
263 fclk=90999000UL; in cx24110_set_symbolrate()
265 dprintk("cx24110 debug: fclk %d Hz\n",fclk); in cx24110_set_symbolrate()
275 BDRI=fclk>>2; in cx24110_set_symbolrate()
288 dprintk("fclk = %d\n", fclk); in cx24110_set_symbolrate()
A Dmb86a20s.h22 u32 fclk; member
/linux/drivers/clk/nuvoton/
A Dclk-ma35d1-pll.c146 unsigned long tmp, fout, fclk, diff; in ma35d1_pll_find_closest() local
153 fclk = div_u64(parent_rate * n, m); in ma35d1_pll_find_closest()
156 fclk = div_u64(fclk, 100); in ma35d1_pll_find_closest()
158 if (fclk < PLL_FCLK_MIN_FREQ || in ma35d1_pll_find_closest()
159 fclk > PLL_FCLK_MAX_FREQ) in ma35d1_pll_find_closest()
162 fout = div_u64(fclk, p); in ma35d1_pll_find_closest()
/linux/arch/sh/drivers/pci/
A Dpcie-sh7786.c26 struct clk *fclk, phy_clk; member
224 port->fclk = clk_get(NULL, fclk_name); in pcie_clk_init()
225 if (IS_ERR(port->fclk)) { in pcie_clk_init()
226 ret = PTR_ERR(port->fclk); in pcie_clk_init()
230 clk_enable(port->fclk); in pcie_clk_init()
250 clk_disable(port->fclk); in pcie_clk_init()
251 clk_put(port->fclk); in pcie_clk_init()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/
A Ddml2_dpmm_dcn4.c24 double *fclk, in get_minimum_clocks_for_latency() argument
35 *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; in get_minimum_clocks_for_latency()
286 display_cfg->min_clocks.dcn4x.active.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
289 display_cfg->min_clocks.dcn4x.active.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
300 display_cfg->min_clocks.dcn4x.idle.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
303 display_cfg->min_clocks.dcn4x.idle.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
332 if (state_table->fclk.num_clk_values == 2) { in map_min_clocks_to_dpm()
336 if (state_table->fclk.num_clk_values == state_table->dcfclk.num_clk_values && in map_min_clocks_to_dpm()
337 state_table->fclk.num_clk_values == state_table->uclk.num_clk_values) { in map_min_clocks_to_dpm()
545 ….dcn4x.active.fclk_khz = in_out->soc_bb->clk_table.fclk.clk_values_khz[in_out->soc_bb->clk_table.f… in clamp_fclk_to_max()
[all …]
/linux/drivers/clocksource/
A Dtimer-ti-dm.c122 struct clk *fclk; member
417 if (unlikely(!timer) || IS_ERR(timer->fclk)) in omap_dm_timer_set_source()
456 ret = clk_set_parent(timer->fclk, parent); in omap_dm_timer_set_source()
728 if (timer && !IS_ERR(timer->fclk)) in omap_dm_timer_get_fclk()
729 return timer->fclk; in omap_dm_timer_get_fclk()
1135 timer->fclk = devm_clk_get(dev, "fck"); in omap_dm_timer_probe()
1136 if (IS_ERR(timer->fclk)) in omap_dm_timer_probe()
1137 return PTR_ERR(timer->fclk); in omap_dm_timer_probe()
1140 ret = devm_clk_notifier_register(dev, timer->fclk, in omap_dm_timer_probe()
1145 timer->fclk_rate = clk_get_rate(timer->fclk); in omap_dm_timer_probe()
[all …]
/linux/drivers/iio/adc/
A Dad7124.c266 unsigned int fclk, odr_sel_bits; in ad7124_set_channel_odr() local
268 fclk = clk_get_rate(st->mclk); in ad7124_set_channel_odr()
276 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); in ad7124_set_channel_odr()
286 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); in ad7124_set_channel_odr()
882 unsigned int fclk, power_mode; in ad7124_setup() local
885 fclk = clk_get_rate(st->mclk); in ad7124_setup()
886 if (!fclk) in ad7124_setup()
892 fclk); in ad7124_setup()
893 if (fclk != ad7124_master_clk_freq_hz[power_mode]) { in ad7124_setup()
894 ret = clk_set_rate(st->mclk, fclk); in ad7124_setup()
A Dad7192.c208 u32 fclk; member
509 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
521 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
522 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
535 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_clock_setup()
551 st->fclk = clk_get_rate(st->mclk); in ad7192_clock_setup()
552 if (!ad7192_valid_external_frequency(st->fclk)) in ad7192_clock_setup()
756 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_compute_f_adc()
764 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_f_adc()
985 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); in ad7192_write_raw()
/linux/drivers/pwm/
A Dpwm-omap-dmtimer.c154 struct clk *fclk; in pwm_omap_dmtimer_config() local
163 fclk = omap->pdata->get_fclk(omap->dm_timer); in pwm_omap_dmtimer_config()
164 if (!fclk) { in pwm_omap_dmtimer_config()
169 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
/linux/drivers/i2c/busses/
A Di2c-omap.c355 struct clk *fclk; in omap_i2c_init() local
374 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
375 if (IS_ERR(fclk)) { in omap_i2c_init()
376 error = PTR_ERR(fclk); in omap_i2c_init()
382 fclk_rate = clk_get_rate(fclk); in omap_i2c_init()
383 clk_put(fclk); in omap_i2c_init()
413 fclk = clk_get(omap->dev, "fck"); in omap_i2c_init()
414 if (IS_ERR(fclk)) { in omap_i2c_init()
415 error = PTR_ERR(fclk); in omap_i2c_init()
420 fclk_rate = clk_get_rate(fclk) / 1000; in omap_i2c_init()
[all …]
/linux/sound/soc/ti/
A Domap-dmic.c36 struct clk *fclk; member
330 mux = clk_get_parent(dmic->fclk); in omap_dmic_select_fclk()
476 dmic->fclk = devm_clk_get(dmic->dev, "fck"); in asoc_dmic_probe()
477 if (IS_ERR(dmic->fclk)) { in asoc_dmic_probe()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c575 if (clock_table->DfPstateTable[i].fclk != 0) { in vg_clk_mgr_helper_populate_bw_params()
590 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
595 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
632 { .fclk = 400, .memclk = 400, .voltage = 2800 },
633 { .fclk = 400, .memclk = 400, .voltage = 2800 },
634 { .fclk = 400, .memclk = 400, .voltage = 2800 },
635 { .fclk = 400, .memclk = 400, .voltage = 2800 }
/linux/drivers/net/hamradio/
A Dbaycom_epp.c167 unsigned int fclk; member
306 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps, in eppconfig()
307 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps), in eppconfig()
984 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0); in baycom_setmode()
985 if (bc->cfg.fclk < 1000000) in baycom_setmode()
986 bc->cfg.fclk = 1000000; in baycom_setmode()
987 if (bc->cfg.fclk > 25000000) in baycom_setmode()
988 bc->cfg.fclk = 25000000; in baycom_setmode()
1083 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps, in baycom_siocdevprivate()
1207 bc->cfg.fclk = 19666600; in baycom_epp_dev_setup()
/linux/drivers/mmc/host/
A Domap.c131 struct clk * fclk; member
194 clk_enable(host->fclk); in mmc_omap_fclk_enable()
196 clk_disable(host->fclk); in mmc_omap_fclk_enable()
1430 host->fclk = clk_get(&pdev->dev, "fck"); in mmc_omap_probe()
1431 if (IS_ERR(host->fclk)) { in mmc_omap_probe()
1432 ret = PTR_ERR(host->fclk); in mmc_omap_probe()
1436 ret = clk_prepare(host->fclk); in mmc_omap_probe()
1510 clk_unprepare(host->fclk); in mmc_omap_probe()
1512 clk_put(host->fclk); in mmc_omap_probe()
1534 clk_unprepare(host->fclk); in mmc_omap_remove()
[all …]
/linux/Documentation/devicetree/bindings/mmc/
A Dti-omap-hsmmc.txt92 swakeup | | fclk
98 In suspend the fclk is off and the module is dysfunctional. Even register reads
99 will fail. A small logic in the host will request fclk restore, when an
/linux/drivers/clk/zynq/
A Dclkc.c103 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, in zynq_clk_register_fclk() argument
147 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
152 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
154 fclk - fclk0); in zynq_clk_register_fclk()
171 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()

Completed in 62 milliseconds

1234