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Searched refs:final_offset (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/display/
A Ddrm_dsc_helper.c209 pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); in drm_dsc_pps_payload_pack()
1371 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()
1375 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { in drm_dsc_compute_rc_parameters()
1381 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); in drm_dsc_compute_rc_parameters()
1410 (vdsc_cfg->final_offset * (1 << 11)) / in drm_dsc_compute_rc_parameters()
1499 cfg->initial_offset, cfg->final_offset, cfg->slice_bpg_offset); in drm_dsc_dump_config_main_params()
/linux/include/drm/display/
A Ddrm_dsc.h219 u16 final_offset; member
447 __be16 final_offset; member
/linux/drivers/gpu/drm/amd/display/dc/dsc/
A Drc_calc_dpi.c64 to->final_offset = from->final_offset; in copy_pps_fields()
/linux/drivers/gpu/drm/i915/display/
A Dintel_vdsc_regs.h145 #define DSC_PPS8_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \ argument
146 final_offset)
A Dintel_vdsc.c499 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) | in intel_dsc_pps_configure()
909 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp); in intel_dsc_get_pps_config()
A Dintel_display.c5465 PIPE_CONF_CHECK_I(dsc.config.final_offset); in intel_pipe_config_compare()
/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_dsc.c107 data |= dsc->final_offset; in dpu_hw_dsc_config()
A Ddpu_hw_dsc_1_2.c194 ((dsc->final_offset & 0xffff) << 16); in dpu_hw_dsc_config_1_2()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
A Ddcn20_dsc.c316 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); in dsc_log_pps()
556 reg_vals->pps.final_offset = 0; in dsc_init_reg_values()
679 FINAL_OFFSET, reg_vals->pps.final_offset); in dsc_write_to_registers()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.c319 FINAL_OFFSET, reg_vals->pps.final_offset); in dsc_write_to_registers()

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