| /linux/drivers/nvmem/ |
| A D | apple-efuses.c | 15 void __iomem *fuses; member
25 *dst++ = readl_relaxed(priv->fuses + offset); in apple_efuses_read()
53 priv->fuses = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in apple_efuses_probe()
54 if (IS_ERR(priv->fuses)) in apple_efuses_probe()
55 return PTR_ERR(priv->fuses); in apple_efuses_probe()
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| /linux/drivers/crypto/intel/qat/qat_c3xxx/ |
| A D | adf_c3xxx_hw_data.c | 31 u32 fuses = self->fuses; in get_accel_mask() local
34 accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET; in get_accel_mask()
43 u32 fuses = self->fuses; in get_ae_mask() local
54 return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK; in get_ae_mask()
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| A D | adf_drv.c | 129 &hw_data->fuses); in adf_probe()
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| /linux/drivers/crypto/intel/qat/qat_c62x/ |
| A D | adf_c62x_hw_data.c | 31 u32 fuses = self->fuses; in get_accel_mask() local
34 accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET; in get_accel_mask()
43 u32 fuses = self->fuses; in get_ae_mask() local
54 return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK; in get_ae_mask()
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| A D | adf_drv.c | 129 &hw_data->fuses); in adf_probe()
172 i = (hw_data->fuses & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0; in adf_probe()
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| /linux/drivers/crypto/intel/qat/qat_dh895xcc/ |
| A D | adf_dh895xcc_hw_data.c | 32 u32 fuses = self->fuses; in get_accel_mask() local
34 return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & in get_accel_mask()
40 u32 fuses = self->fuses; in get_ae_mask() local
42 return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK; in get_ae_mask()
102 int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK) in get_sku()
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| A D | adf_drv.c | 129 &hw_data->fuses); in adf_probe()
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| /linux/drivers/pmdomain/qcom/ |
| A D | cpr.c | 804 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_populate_ring_osc_idx() local
808 for (; fuse < end; fuse++, fuses++) { in cpr_populate_ring_osc_idx()
846 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_fuse_corner_init() local
1166 quot_offset = fuses[fnum].quotient_offset; in cpr_corner_init()
1219 struct cpr_fuse *fuses; in cpr_get_fuses() local
1225 if (!fuses) in cpr_get_fuses()
1233 if (!fuses[i].ring_osc) in cpr_get_fuses()
1239 if (!fuses[i].init_voltage) in cpr_get_fuses()
1244 if (!fuses[i].quotient) in cpr_get_fuses()
1250 if (!fuses[i].quotient_offset) in cpr_get_fuses()
[all …]
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| /linux/drivers/crypto/intel/qat/qat_common/ |
| A D | adf_gen2_hw_data.c | 119 u32 fuses = hw_data->fuses; in adf_gen2_get_accel_cap() local
144 if ((straps | fuses) & ADF_POWERGATE_PKE) in adf_gen2_get_accel_cap()
147 if ((straps | fuses) & ADF_POWERGATE_DC) in adf_gen2_get_accel_cap()
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| A D | adf_accel_devices.h | 346 u32 fuses; member
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| /linux/Documentation/devicetree/bindings/cpufreq/ |
| A D | imx-cpufreq-dt.txt | 5 "speed grading" value which are written in fuses. These bits are combined with
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| /linux/Documentation/devicetree/bindings/phy/ |
| A D | nvidia,tegra20-usb-phy.yaml | 167 nvidia,xcvr-setup-use-fuses:
168 description: Indicates that the value is read from the on-chip fuses.
254 - required: ["nvidia,xcvr-setup-use-fuses"]
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| /linux/Documentation/devicetree/bindings/iio/adc/ |
| A D | microchip,mcp3564.yaml | 84 The address is set on a per-device basis by fuses in the factory,
85 configured on request. If not requested, the fuses are set for 0x1.
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| /linux/drivers/crypto/intel/qat/qat_420xx/ |
| A D | adf_drv.c | 82 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses); in adf_probe()
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| A D | adf_420xx_hw_data.c | 101 u32 me_disable = self->fuses; in get_ae_mask()
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| /linux/drivers/crypto/intel/qat/qat_4xxx/ |
| A D | adf_drv.c | 84 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses); in adf_probe()
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| A D | adf_4xxx_hw_data.c | 104 u32 me_disable = self->fuses; in get_ae_mask()
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| /linux/arch/arm/boot/dts/nvidia/ |
| A D | tegra30-asus-tf201.dts | 590 /delete-property/ nvidia,xcvr-setup-use-fuses;
595 /delete-property/ nvidia,xcvr-setup-use-fuses;
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| A D | tegra30.dtsi | 1143 nvidia,xcvr-setup-use-fuses;
1186 nvidia,xcvr-setup-use-fuses;
1228 nvidia,xcvr-setup-use-fuses;
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| A D | tegra20-asus-tf101.dts | 880 nvidia,xcvr-setup-use-fuses;
893 nvidia,xcvr-setup-use-fuses;
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| A D | tegra20-acer-a500-picasso.dts | 1107 nvidia,xcvr-setup-use-fuses;
1118 nvidia,xcvr-setup-use-fuses;
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| /linux/drivers/nvme/target/ |
| A D | passthru.c | 138 id->fuses = 0; in nvmet_passthru_override_id_ctrl()
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| /linux/Documentation/security/keys/ |
| A D | trusted-encrypted.rst | 36 fuses and is accessible to TEE only.
48 in the on-chip fuses and is accessible to the DCP encryption engine only.
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| /linux/include/linux/ |
| A D | nvme.h | 341 __le16 fuses; member
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| /linux/arch/arm64/boot/dts/freescale/ |
| A D | imx8mn.dtsi | 585 * reg = <0x4 0x8> describes fuses 0x410 and
|