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Searched refs:fw_based_mclk_switching (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c710 …clk_mgr_base->clks.fw_based_mclk_switching = p_state_change_support && new_clocks->fw_based_mclk_s… in dcn401_update_clocks_legacy()
1035 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching && in dcn401_build_update_bandwidth_clocks_sequence()
1036 new_clocks->fw_based_mclk_switching) { in dcn401_build_update_bandwidth_clocks_sequence()
1038 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
1040 …_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
1044 ….params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
1191 if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching && in dcn401_build_update_bandwidth_clocks_sequence()
1192 safe_to_lower && !new_clocks->fw_based_mclk_switching) { in dcn401_build_update_bandwidth_clocks_sequence()
1194 clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
1196 …_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching; in dcn401_build_update_bandwidth_clocks_sequence()
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c371 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
394 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
405 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = in dcn30_fpu_calculate_wm_and_dlg()
408 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
498 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
573 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && in dcn30_fpu_calculate_wm_and_dlg()
593 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn30_fpu_calculate_wm_and_dlg()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.c1152 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) && in dcn30_hardware_release()
1173 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switchi… in dcn30_prepare_bandwidth()
1185 if (!dc->clk_mgr->clks.fw_based_mclk_switching) in dcn30_prepare_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_wrapper.c446 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in optimize_pstate_with_svp_and_drr()
459 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; in optimize_pstate_with_svp_and_drr()
525 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in optimize_pstate_with_svp_and_drr()
A Ddml2_translation_helper.c1155 if (state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in apply_legacy_svp_drr_settings()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1829 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
1841 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn32_prepare_bandwidth()
1844 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.c1668 …xt->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; in dcn32_calculate_dlg_params()
2351 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn32_calculate_wm_and_dlg_fpu()
2368 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; in dcn32_calculate_wm_and_dlg_fpu()
2371 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn32_calculate_wm_and_dlg_fpu()
2402 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn32_calculate_wm_and_dlg_fpu()
2498 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn32_calculate_wm_and_dlg_fpu()
2517 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !subvp_in_use) { in dcn32_calculate_wm_and_dlg_fpu()
3597 if ((context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dcn32_subvp_in_use(dc, context)) && in dcn32_override_min_req_memclk()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_utils.c578 …context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.fe… in dml21_build_fams2_programming()
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_hw_sequencer.c518 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in set_p_state_switch_method()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c729 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn32_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c2418 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn20_optimize_bandwidth()
2422 dc->clk_mgr->clks.fw_based_mclk_switching = true; in dcn20_optimize_bandwidth()
2424 dc->clk_mgr->clks.fw_based_mclk_switching = false; in dcn20_optimize_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c1758 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dml1_validate()
1977 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) in dcn32_populate_dml_pipes_from_context()
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc.h613 bool fw_based_mclk_switching; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1171 …xt->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; in dcn20_calculate_dlg_params()

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