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Searched refs:gate (Results 1 – 25 of 430) sorted by relevance

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/linux/drivers/clk/tegra/
A Dclk-periph-gate.c20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
41 if (!(read_enb(gate) & periph_clk_to_bit(gate))) in clk_periph_is_enabled()
45 if (read_rst(gate) & periph_clk_to_bit(gate)) in clk_periph_is_enabled()
55 write_enb_set(periph_clk_to_bit(gate), gate); in clk_periph_enable_locked()
78 write_enb_clr(periph_clk_to_bit(gate), gate); in clk_periph_disable_locked()
88 if (!gate->enable_refcnt[gate->clk_num]++) in clk_periph_enable()
103 WARN_ON(!gate->enable_refcnt[gate->clk_num]); in clk_periph_disable()
105 if (--gate->enable_refcnt[gate->clk_num] == 0) in clk_periph_disable()
123 if (!gate->enable_refcnt[gate->clk_num]) in clk_periph_disable_unused()
[all …]
/linux/drivers/clk/mmp/
A Dclk-gate.c31 if (gate->lock) in mmp_clk_gate_enable()
39 if (gate->lock) in mmp_clk_gate_enable()
57 if (gate->lock) in mmp_clk_gate_disable()
65 if (gate->lock) in mmp_clk_gate_disable()
75 if (gate->lock) in mmp_clk_gate_is_enabled()
80 if (gate->lock) in mmp_clk_gate_is_enabled()
83 return (tmp & gate->mask) == gate->val_enable; in mmp_clk_gate_is_enabled()
102 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in mmp_clk_register_gate()
103 if (!gate) in mmp_clk_register_gate()
113 gate->reg = reg; in mmp_clk_register_gate()
[all …]
/linux/drivers/clk/imx/
A Dclk-gate-93.c58 val &= ~(gate->mask << gate->bit_idx); in imx93_clk_gate_do_hardware()
60 val |= (gate->val & gate->mask) << gate->bit_idx; in imx93_clk_gate_do_hardware()
72 if (gate->share_count && (*gate->share_count)++ > 0) in imx93_clk_gate_enable()
111 if (((val >> gate->bit_idx) & gate->mask) == gate->val) in imx93_clk_gate_reg_is_enabled()
140 if (!gate->share_count || *gate->share_count == 0) in imx93_clk_gate_disable_unused()
168 if (!gate) in imx93_clk_gate()
171 gate->reg = reg; in imx93_clk_gate()
174 gate->val = val; in imx93_clk_gate()
175 gate->mask = mask; in imx93_clk_gate()
185 hw = &gate->hw; in imx93_clk_gate()
[all …]
A Dclk-gate2.c47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
60 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
108 ret = clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, in clk_gate2_is_enabled()
109 gate->cgr_val, gate->cgr_mask); in clk_gate2_is_enabled()
123 if (!gate->share_count || *gate->share_count == 0) in clk_gate2_disable_unused()
148 if (!gate) in clk_hw_register_gate2()
152 gate->reg = reg; in clk_hw_register_gate2()
157 gate->lock = lock; in clk_hw_register_gate2()
167 hw = &gate->hw; in clk_hw_register_gate2()
[all …]
A Dclk-gate-exclusive.c25 struct clk_gate gate; member
33 struct clk_gate_exclusive, gate); in clk_gate_exclusive_enable()
34 u32 val = readl(gate->reg); in clk_gate_exclusive_enable()
62 struct clk_gate *gate; in imx_clk_hw_gate_exclusive() local
73 gate = &exgate->gate; in imx_clk_hw_gate_exclusive()
81 gate->reg = reg; in imx_clk_hw_gate_exclusive()
82 gate->bit_idx = shift; in imx_clk_hw_gate_exclusive()
83 gate->lock = &imx_ccm_lock; in imx_clk_hw_gate_exclusive()
84 gate->hw.init = &init; in imx_clk_hw_gate_exclusive()
87 hw = &gate->hw; in imx_clk_hw_gate_exclusive()
[all …]
A Dclk-composite-93.c52 if (gate->lock) in imx93_clk_composite_gate_endisable()
55 reg = readl(gate->reg); in imx93_clk_composite_gate_endisable()
58 reg &= ~BIT(gate->bit_idx); in imx93_clk_composite_gate_endisable()
60 reg |= BIT(gate->bit_idx); in imx93_clk_composite_gate_endisable()
62 writel(reg, gate->reg); in imx93_clk_composite_gate_endisable()
66 if (gate->lock) in imx93_clk_composite_gate_endisable()
233 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in imx93_clk_composite_flags()
234 if (!gate) in imx93_clk_composite_flags()
237 gate_hw = &gate->hw; in imx93_clk_composite_flags()
238 gate->reg = reg; in imx93_clk_composite_flags()
[all …]
A Dclk-composite-7ulp.c39 spin_lock_irqsave(gate->lock, flags); in pcc_gate_enable()
44 val = readl(gate->reg); in pcc_gate_enable()
46 writel(val, gate->reg); in pcc_gate_enable()
77 struct clk_gate *gate = NULL; in imx_ulp_clk_hw_composite() local
118 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in imx_ulp_clk_hw_composite()
119 if (!gate) { in imx_ulp_clk_hw_composite()
124 gate_hw = &gate->hw; in imx_ulp_clk_hw_composite()
125 gate->reg = reg; in imx_ulp_clk_hw_composite()
126 gate->bit_idx = PCG_CGC_SHIFT; in imx_ulp_clk_hw_composite()
128 gate->lock = &imx_ccm_lock; in imx_ulp_clk_hw_composite()
[all …]
/linux/drivers/clk/
A Dclk-gate.c32 return readl(gate->reg); in clk_gate_readl()
65 if (gate->lock) in clk_gate_endisable()
85 if (gate->lock) in clk_gate_endisable()
148 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in __clk_hw_register_gate()
149 if (!gate) in __clk_hw_register_gate()
164 gate->reg = reg; in __clk_hw_register_gate()
167 gate->lock = lock; in __clk_hw_register_gate()
170 hw = &gate->hw; in __clk_hw_register_gate()
176 kfree(gate); in __clk_hw_register_gate()
212 kfree(gate); in clk_unregister_gate()
[all …]
A Dclk-ast2600.c302 regmap_read(gate->map, get_reset_reg(gate), &reg); in aspeed_g6_clk_is_enabled()
308 regmap_read(gate->map, get_clock_reg(gate), &reg); in aspeed_g6_clk_is_enabled()
331 regmap_write(gate->map, get_reset_reg(gate), rst); in aspeed_g6_clk_enable()
339 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk); in aspeed_g6_clk_enable()
342 regmap_write(gate->map, get_clock_reg(gate), clk); in aspeed_g6_clk_enable()
349 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst); in aspeed_g6_clk_enable()
366 regmap_write(gate->map, get_clock_reg(gate), clk); in aspeed_g6_clk_disable()
369 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk); in aspeed_g6_clk_disable()
434 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in aspeed_g6_clk_hw_register_gate()
435 if (!gate) in aspeed_g6_clk_hw_register_gate()
[all …]
/linux/drivers/staging/sm750fb/
A Dddk750_power.c78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
101 u32 gate; in sm750_enable_dma() local
106 gate |= CURRENT_GATE_DMA; in sm750_enable_dma()
108 gate &= ~CURRENT_GATE_DMA; in sm750_enable_dma()
118 u32 gate; in sm750_enable_gpio() local
123 gate |= CURRENT_GATE_GPIO; in sm750_enable_gpio()
135 u32 gate; in sm750_enable_i2c() local
140 gate |= CURRENT_GATE_I2C; in sm750_enable_i2c()
[all …]
/linux/drivers/clk/visconti/
A Dclkc.c31 u32 clk = BIT(gate->ck_idx); in visconti_gate_clk_is_enabled()
34 regmap_read(gate->regmap, gate->ckon_offset, &val); in visconti_gate_clk_is_enabled()
51 regmap_update_bits(gate->regmap, gate->ckoff_offset, clk, clk); in visconti_gate_clk_disable()
62 regmap_update_bits(gate->regmap, gate->ckon_offset, clk, clk); in visconti_gate_clk_enable()
96 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); in visconti_clk_register_gate()
97 if (!gate) in visconti_clk_register_gate()
106 gate->regmap = regmap; in visconti_clk_register_gate()
112 gate->rs_idx = rs_idx; in visconti_clk_register_gate()
113 gate->lock = lock; in visconti_clk_register_gate()
114 gate->hw.init = &init; in visconti_clk_register_gate()
[all …]
/linux/drivers/clk/uniphier/
A Dclk-uniphier-gate.c27 return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), in uniphier_clk_gate_endisable()
28 enable ? BIT(gate->bit) : 0); in uniphier_clk_gate_endisable()
47 if (regmap_read(gate->regmap, gate->reg, &val) < 0) in uniphier_clk_gate_is_enabled()
64 struct uniphier_clk_gate *gate; in uniphier_clk_register_gate() local
68 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); in uniphier_clk_register_gate()
69 if (!gate) in uniphier_clk_register_gate()
78 gate->regmap = regmap; in uniphier_clk_register_gate()
79 gate->reg = data->reg; in uniphier_clk_register_gate()
80 gate->bit = data->bit; in uniphier_clk_register_gate()
81 gate->hw.init = &init; in uniphier_clk_register_gate()
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
A Dgate.txt1 Binding for Texas Instruments gate clock.
16 "ti,gate-clock" - basic gate clock
17 "ti,wait-gate-clock" - gate clock which waits until clock is active before
19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
20 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
21 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
24 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
26 "ti,composite-gate-clock" - composite gate clock, to be part of composite
28 "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
34 ti,clkdm-gate-clock type
[all …]
/linux/drivers/clk/ingenic/
A Djz4755-cgu.c144 .gate = { CGU_REG_CLKGR, 10 },
151 .gate = { CGU_REG_CLKGR, 9 },
171 .gate = { CGU_REG_CLKGR, 4 },
185 .gate = { CGU_REG_CLKGR, 2 },
192 .gate = { CGU_REG_CLKGR, 8 },
200 .gate = { CGU_REG_CLKGR, 0 },
218 .gate = { CGU_REG_CLKGR, 7 },
224 .gate = { CGU_REG_CLKGR, 5 },
230 .gate = { CGU_REG_CLKGR, 3 },
242 .gate = { CGU_REG_CLKGR, 1 },
[all …]
A Djz4770-cgu.c178 .gate = { CGU_REG_CLKGR1, 7 },
234 .gate = { CGU_REG_CLKGR0, 26 },
248 .gate = { CGU_REG_CLKGR1, 9 },
255 .gate = { CGU_REG_CLKGR0, 1 },
302 .gate = { CGU_REG_CLKGR0, 2 },
310 .gate = { CGU_REG_CLKGR0, 4 },
325 .gate = { CGU_REG_CLKGR1, 8 },
340 .gate = { CGU_REG_CLKGR1, 0 },
345 .gate = { CGU_REG_CLKGR0, 5 },
350 .gate = { CGU_REG_CLKGR0, 6 },
[all …]
A Djz4760-cgu.c219 .gate = { CGU_REG_CLKGR0, 24 },
226 .gate = { CGU_REG_CLKGR1, 9 },
238 .gate = { CGU_REG_CLKGR0, 27 },
262 .gate = { CGU_REG_CLKGR1, 8 },
277 .gate = { CGU_REG_CLKGR0, 2 },
307 .gate = { CGU_REG_CLKGR0, 4 },
332 .gate = { CGU_REG_CLKGR1, 0 },
337 .gate = { CGU_REG_CLKGR0, 5 },
342 .gate = { CGU_REG_CLKGR0, 6 },
377 .gate = { CGU_REG_CLKGR0, 8 },
[all …]
A Djz4780-cgu.c409 .gate = { CGU_REG_CLKGR1, 2 },
451 .gate = { CGU_REG_CLKGR0, 3 },
509 .gate = { CGU_REG_CLKGR1, 3 },
518 .gate = { CGU_REG_CLKGR1, 4 },
527 .gate = { CGU_REG_CLKGR1, 9 },
536 .gate = { CGU_REG_CLKGR0, 1 },
556 .gate = { CGU_REG_CLKGR0, 0 },
562 .gate = { CGU_REG_CLKGR0, 2 },
568 .gate = { CGU_REG_CLKGR0, 4 },
574 .gate = { CGU_REG_CLKGR0, 5 },
[all …]
A Dx1830-cgu.c231 .gate = { CGU_REG_CLKGR1, 15 },
290 .gate = { CGU_REG_CLKGR1, 4 },
299 .gate = { CGU_REG_CLKGR1, 9 },
313 .gate = { CGU_REG_CLKGR0, 4 },
320 .gate = { CGU_REG_CLKGR0, 5 },
361 .gate = { CGU_REG_CLKGR0, 0 },
367 .gate = { CGU_REG_CLKGR0, 1 },
373 .gate = { CGU_REG_CLKGR0, 3 },
379 .gate = { CGU_REG_CLKGR0, 6 },
385 .gate = { CGU_REG_CLKGR0, 7 },
[all …]
A Djz4740-cgu.c156 .gate = { CGU_REG_CLKGR, 10 },
170 .gate = { CGU_REG_CLKGR, 6 },
178 .gate = { CGU_REG_CLKGR, 4 },
185 .gate = { CGU_REG_CLKGR, 7 },
192 .gate = { CGU_REG_CLKGR, 14 },
208 .gate = { CGU_REG_CLKGR, 0 },
214 .gate = { CGU_REG_CLKGR, 15 },
232 .gate = { CGU_REG_CLKGR, 8 },
238 .gate = { CGU_REG_CLKGR, 3 },
244 .gate = { CGU_REG_CLKGR, 5 },
[all …]
/linux/Documentation/devicetree/bindings/clock/
A Dsprd,sc9860-clk.yaml17 - sprd,sc9860-agcp-gate
19 - sprd,sc9860-aon-gate
21 - sprd,sc9860-apahb-gate
22 - sprd,sc9860-apapb-gate
25 - sprd,sc9860-cam-gate
27 - sprd,sc9860-disp-gate
30 - sprd,sc9860-pmu-gate
32 - sprd,sc9860-vsp-gate
62 - sprd,sc9860-aon-gate
65 - sprd,sc9860-cam-gate
[all …]
/linux/drivers/clk/zynqmp/
A Dclk-gate-zynqmp.c38 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_enable()
58 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_disable()
78 u32 clk_id = gate->clk_id; in zynqmp_clk_gate_is_enabled()
112 struct zynqmp_clk_gate *gate; in zynqmp_clk_register_gate() local
118 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in zynqmp_clk_register_gate()
119 if (!gate) in zynqmp_clk_register_gate()
131 gate->flags = nodes->type_flag; in zynqmp_clk_register_gate()
132 gate->hw.init = &init; in zynqmp_clk_register_gate()
133 gate->clk_id = clk_id; in zynqmp_clk_register_gate()
135 hw = &gate->hw; in zynqmp_clk_register_gate()
[all …]
/linux/drivers/clk/bcm/
A Dclk-kona.c356 if (!gate_exists(gate)) in __is_clk_gate_enabled()
373 if (!gate_exists(gate)) in is_clk_gate_enabled()
417 if (gate_is_sw_managed(gate) && (enabled = gate_is_enabled(gate)) && in __gate_commit()
430 return __ccu_wait_bit(ccu, gate->offset, gate->status_bit, enabled); in __gate_commit()
441 if (!gate_exists(gate)) in gate_init()
457 if (!gate_exists(gate) || !gate_is_sw_managed(gate)) in __clk_gate()
469 gate_flip_enabled(gate); in __clk_gate()
488 if (!gate_exists(gate) || !gate_is_sw_managed(gate)) in clk_gate()
969 struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate; in kona_peri_clk_enable() local
977 struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate; in kona_peri_clk_disable() local
[all …]
A Dclk-bcm281xx.c16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
34 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
43 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
76 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
95 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
107 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
119 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
131 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
143 .gate = HW_SW_GATE(0x0354, 18, 2, 3),
154 .gate = HW_SW_GATE(0x0370, 18, 2, 3),
[all …]
A Dclk-bcm21664.c16 .gate = HW_SW_GATE(0x214, 16, 0, 1),
33 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
58 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
70 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
82 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
94 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
107 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
112 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
117 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
122 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
[all …]
/linux/drivers/clk/mediatek/
A Dclk-gate.c223 const struct mtk_gate *gate = &clks[i]; in mtk_clk_register_gates() local
227 node, gate->id); in mtk_clk_register_gates()
231 hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name, in mtk_clk_register_gates()
233 gate->regs->set_ofs, in mtk_clk_register_gates()
234 gate->regs->clr_ofs, in mtk_clk_register_gates()
235 gate->regs->sta_ofs, in mtk_clk_register_gates()
236 gate->shift, gate->ops, in mtk_clk_register_gates()
237 gate->flags); in mtk_clk_register_gates()
245 clk_data->hws[gate->id] = hw; in mtk_clk_register_gates()
252 const struct mtk_gate *gate = &clks[i]; in mtk_clk_register_gates() local
[all …]

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