| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| A D | dcn30_hubp.c | 325 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp3_program_tiling()
326 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp3_program_tiling()
327 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), in hubp3_program_tiling()
328 NUM_PKRS, log_2(info->gfx9.num_pkrs)); in hubp3_program_tiling()
331 SW_MODE, info->gfx9.swizzle, in hubp3_program_tiling()
332 META_LINEAR, info->gfx9.meta_linear, in hubp3_program_tiling()
333 PIPE_ALIGNED, info->gfx9.pipe_aligned); in hubp3_program_tiling()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| A D | dcn10_hubp.c | 149 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp1_program_tiling()
150 NUM_BANKS, log_2(info->gfx9.num_banks), in hubp1_program_tiling()
151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp1_program_tiling()
152 NUM_SE, log_2(info->gfx9.num_shader_engines), in hubp1_program_tiling()
153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), in hubp1_program_tiling()
154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); in hubp1_program_tiling()
157 SW_MODE, info->gfx9.swizzle, in hubp1_program_tiling()
158 META_LINEAR, info->gfx9.meta_linear, in hubp1_program_tiling()
159 RB_ALIGNED, info->gfx9.rb_aligned, in hubp1_program_tiling()
160 PIPE_ALIGNED, info->gfx9.pipe_aligned); in hubp1_program_tiling()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_plane.c | 215 tiling_info->gfx9.num_pipes = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
217 tiling_info->gfx9.num_banks = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
219 tiling_info->gfx9.pipe_interleave = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
221 tiling_info->gfx9.num_shader_engines = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
223 tiling_info->gfx9.max_compressed_frags = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
225 tiling_info->gfx9.num_rb_per_se = in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
227 tiling_info->gfx9.shaderEnable = 1; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_device()
248 tiling_info->gfx9.num_pipes = 1u << pipes_log2; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier()
252 tiling_info->gfx9.num_pkrs = 1u << pkrs_log2; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier()
254 tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits; in amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier()
[all …]
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| A D | amdgpu_dm_trace.h | 450 __entry->swizzle = plane_state->tiling_info.gfx9.swizzle;
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| A D | amdgpu_dm.c | 7272 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; in dm_validate_stream_and_context()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_mem_input.c | 437 GRPH_SW_MODE, info->gfx9.swizzle, in program_tiling()
438 GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), in program_tiling()
439 GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines), in program_tiling()
440 GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes), in program_tiling()
442 GRPH_SE_ENABLE, info->gfx9.shaderEnable); in program_tiling()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_debug.c | 172 plane_state->tiling_info.gfx9.swizzle); in pre_surface_trace()
258 update->plane_info->tiling_info.gfx9.swizzle); in update_surface_trace()
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| A D | dc_hw_sequencer.c | 972 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { in get_surface_tile_visual_confirm_color()
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| A D | dc_resource.c | 4064 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/ |
| A D | dcn20_hubp.c | 317 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp2_program_tiling()
318 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp2_program_tiling()
319 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); in hubp2_program_tiling()
322 SW_MODE, info->gfx9.swizzle, in hubp2_program_tiling()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_hw_types.h | 423 } gfx9;/*gfx9, gfx10 and above*/ member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
348 …input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.s… in pipe_ctx_to_e2e_pipe_params()
1010 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource_helpers.c | 404 …if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swiz… in dcn32_set_det_allocations()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 2231 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S; in dcn20_patch_unknown_plane_state()
2233 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D; in dcn20_patch_unknown_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 1235 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_patch_unknown_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1687 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
1688 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 688 surface->tiling = gfx9_to_dml2_swizzle_mode(plane_state->tiling_info.gfx9.swizzle); in populate_dml21_surface_config_from_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_translation_helper.c | 885 out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle; in populate_dml_surface_cfg_from_plane_state()
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