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Searched refs:gpu_addr (Results 1 – 25 of 174) sorted by relevance

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/linux/drivers/gpu/drm/radeon/
A Dr600_dma.c150 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
236 u64 gpu_addr; in r600_dma_ring_test() local
243 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ring_test()
254 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
290 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
317 u64 addr = semaphore->gpu_addr; in r600_dma_semaphore_ring_emit()
343 u64 gpu_addr; in r600_dma_ib_test() local
350 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ib_test()
359 ib.ptr[1] = lower_32_bits(gpu_addr); in r600_dma_ib_test()
360 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test()
[all …]
A Duvd_v4_2.c47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume()
49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
A Dcik_sdma.c155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
232 u64 addr = semaphore->gpu_addr; in cik_sdma_semaphore_ring_emit()
651 u64 gpu_addr; in cik_sdma_ring_test() local
658 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ring_test()
669 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test()
670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
708 u64 gpu_addr; in cik_sdma_ib_test() local
715 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ib_test()
727 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ib_test()
[all …]
A Duvd_v2_2.c43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit()
113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
A Duvd_v1_0.c85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit()
121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
364 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | in uvd_v1_0_start()
374 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); in uvd_v1_0_start()
487 radeon_ring_write(ring, ib->gpu_addr); in uvd_v1_0_ib_execute()
A Dradeon_semaphore.c51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create()
69 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_emit_signal()
86 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_emit_wait()
A Dvce_v1_0.c218 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume()
300 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); in vce_v1_0_start()
301 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
307 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); in vce_v1_0_start()
308 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_ih.c69 ih->gpu_addr = dma_addr; in amdgpu_ih_ring_init()
89 &ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; in amdgpu_ih_ring_init()
128 (void *)ih->ring, ih->gpu_addr); in amdgpu_ih_ring_fini()
131 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, in amdgpu_ih_ring_fini()
133 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
134 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
A Dvcn_v2_0.c393 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
950 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_0_start_dpg_mode()
954 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
956 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
1114 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1116 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1836 uint64_t addr = table->gpu_addr; in vcn_v2_0_start_mmsch()
1998 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2001 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
2012 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_sriov()
[all …]
A Dvce_v4_0.c157 uint64_t addr = table->gpu_addr; in vce_v4_0_mmsch_start()
235 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
237 upper_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
263 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
266 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
273 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
276 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
279 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
282 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
658 (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
[all …]
A Dvcn_v2_5.c481 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
986 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_5_start_dpg_mode()
990 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
992 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1170 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1172 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1208 uint64_t addr = table->gpu_addr; in vcn_v2_5_mmsch_start()
1358 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1361 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
1371 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_sriov_start()
[all …]
A Dsi_dma.c74 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
158 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in si_dma_start()
199 u64 gpu_addr; in si_dma_ring_test_ring() local
205 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ring()
214 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
215 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring()
250 u64 gpu_addr; in si_dma_ring_test_ib() local
257 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ib()
267 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
268 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
[all …]
A Damdgpu_sa.c54 &sa_manager->bo, &sa_manager->gpu_addr, in amdgpu_sa_bo_manager_init()
76 amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr); in amdgpu_sa_bo_manager_fini()
114 drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr); in amdgpu_sa_bo_dump_debug_info()
A Dvcn_v4_0_3.c400 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); in vcn_v4_0_3_mc_resume()
403 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); in vcn_v4_0_3_mc_resume()
866 lower_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start_dpg_mode()
868 upper_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start_dpg_mode()
961 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_3_start_sriov()
964 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_3_start_sriov()
975 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; in vcn_v4_0_3_start_sriov()
1005 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_3_start_sriov()
1034 ctx_addr = table->gpu_addr; in vcn_v4_0_3_start_sriov()
1230 lower_32_bits(ring->gpu_addr)); in vcn_v4_0_3_start()
[all …]
A Dvcn_v1_0.c361 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
363 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
965 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_spg_mode()
969 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
971 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1123 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_dpg_mode()
1127 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1129 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1354 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1356 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
[all …]
A Dvcn_v4_0.c440 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
442 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_mc_resume()
450 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
452 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_mc_resume()
466 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_mc_resume()
1353 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov()
1356 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v4_0_start_sriov()
1367 cache_addr = adev->vcn.inst[i].gpu_addr + offset; in vcn_v4_0_start_sriov()
1381 cache_addr = adev->vcn.inst[i].gpu_addr + offset + in vcn_v4_0_start_sriov()
1401 rb_enc_addr = ring_enc->gpu_addr; in vcn_v4_0_start_sriov()
[all …]
A Dvcn_v3_0.c508 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
1108 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v3_0_start_dpg_mode()
1112 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1114 upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1289 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1291 upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1394 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1397 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v3_0_start_sriov()
1440 rb_addr = ring->gpu_addr; in vcn_v3_0_start_sriov()
1454 rb_addr = ring->gpu_addr; in vcn_v3_0_start_sriov()
[all …]
A Dvce_v3_0.c283 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); in vce_v3_0_start()
284 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
290 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); in vce_v3_0_start()
291 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
297 WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); in vce_v3_0_start()
298 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
567 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
571 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
869 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
870 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
[all …]
A Dvcn_v5_0_0.c352 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_0_mc_resume()
354 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v5_0_0_mc_resume()
362 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_0_mc_resume()
364 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v5_0_0_mc_resume()
378 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_0_mc_resume()
380 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v5_0_0_mc_resume()
426 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
429 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
725 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v5_0_0_start_dpg_mode()
882 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v5_0_0_start()
[all …]
A Duvd_v7_0.c695 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
697 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
735 uint64_t addr = table->gpu_addr; in uvd_v7_0_mmsch_start()
837 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
839 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
1098 (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v7_0_start()
1102 lower_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1104 upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
1334 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
1337 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib()
[all …]
A Damdgpu_seq64.h41 int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, u64 **cpu_addr);
42 void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr);
A Dsdma_v2_4.c258 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
259 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
536 u64 gpu_addr; in sdma_v2_4_ring_test_ring() local
542 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ring()
552 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
553 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
589 u64 gpu_addr; in sdma_v2_4_ring_test_ib() local
596 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ib()
607 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
608 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
[all …]
A Dvcn_v4_0_5.c388 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_5_mc_resume()
390 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v4_0_5_mc_resume()
398 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_5_mc_resume()
400 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v4_0_5_mc_resume()
414 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_5_mc_resume()
416 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v4_0_5_mc_resume()
464 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
467 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
963 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v4_0_5_start_dpg_mode()
1150 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v4_0_5_start()
[all …]
A Dcik_sdma.c234 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
475 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
606 u64 gpu_addr; in cik_sdma_ring_test_ring() local
612 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ring()
621 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
622 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
658 u64 gpu_addr; in cik_sdma_ring_test_ib() local
665 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ib()
676 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
677 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_mqd_manager.c58 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; in allocate_hiq_mqd()
84 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in allocate_sdma_mqd()
285 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; in kfd_get_hiq_xcc_mqd()

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