| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| A D | dcn201_dpp.c | 218 if (in_taps->h_taps == 0) { in dpp201_get_optimal_number_of_taps()
220 scl_data->taps.h_taps = 8; in dpp201_get_optimal_number_of_taps()
222 scl_data->taps.h_taps = 4; in dpp201_get_optimal_number_of_taps()
224 scl_data->taps.h_taps = in_taps->h_taps; in dpp201_get_optimal_number_of_taps()
253 scl_data->taps.h_taps = 1; in dpp201_get_optimal_number_of_taps()
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| /linux/drivers/gpu/drm/amd/display/dc/spl/ |
| A D | dc_spl.c | 622 spl_scratch->scl_data.taps.h_taps, in spl_calculate_inits_and_viewports()
864 if ((taps.h_taps == 4 || taps.h_taps == 6) && in spl_get_isharp_en()
897 if (in_taps->h_taps == 0) { in spl_get_optimal_number_of_taps()
902 spl_scratch->scl_data.taps.h_taps = 4; in spl_get_optimal_number_of_taps()
904 spl_scratch->scl_data.taps.h_taps = in_taps->h_taps; in spl_get_optimal_number_of_taps()
934 spl_scratch->scl_data.taps.h_taps = 6; in spl_get_optimal_number_of_taps()
939 spl_scratch->scl_data.taps.h_taps = 6; in spl_get_optimal_number_of_taps()
1003 spl_scratch->scl_data.taps.h_taps = 4; in spl_get_optimal_number_of_taps()
1053 spl_scratch->scl_data.taps.h_taps = 1; in spl_get_optimal_number_of_taps()
1132 dscl_prog_data->taps.h_taps = scl_data->taps.h_taps - 1; in spl_set_taps_data()
[all …]
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| A D | dc_spl_scl_easf_filters.c | 1495 data->taps.h_taps, data->recip_ratios.horz); in spl_set_filters_data()
1501 data->taps.h_taps, data->ratios.horz); in spl_set_filters_data()
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| A D | dc_spl_isharp_filters.c | 752 spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps); in spl_set_blur_scale_data()
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| A D | dc_spl_types.h | 41 uint32_t h_taps; member
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_transform.c | 122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
132 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
165 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in dce60_setup_scaling_configuration()
294 dc_fixpt_from_int(data->taps.h_taps + 1)), in calculate_inits()
440 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce_transform_set_scaler()
464 data->taps.h_taps, in dce_transform_set_scaler()
469 data->taps.h_taps, in dce_transform_set_scaler()
549 data->taps.h_taps, in dce60_transform_set_scaler()
554 data->taps.h_taps, in dce60_transform_set_scaler()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_display_cfg_types.h | 229 unsigned int h_taps; member
236 unsigned int h_taps; member
302 unsigned long h_taps; member
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_spl_translate.c | 38 spl_scaling_quality->h_taps = scaling_quality->h_taps; in populate_spltaps_from_taps()
46 scaling_quality->h_taps = spl_scaling_quality->h_taps + 1; in populate_taps_from_spltaps()
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| A D | dc_hw_types.h | 699 uint32_t h_taps; member
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| A D | dcn10_dpp.c | 154 if (in_taps->h_taps == 0) in dpp1_get_optimal_number_of_taps()
155 scl_data->taps.h_taps = 4; in dpp1_get_optimal_number_of_taps()
157 scl_data->taps.h_taps = in_taps->h_taps; in dpp1_get_optimal_number_of_taps()
176 scl_data->taps.h_taps = 1; in dpp1_get_optimal_number_of_taps()
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| A D | dcn10_dpp_dscl.c | 295 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
297 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
317 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
338 dpp, scl_data->taps.h_taps, in dpp1_dscl_set_scl_filter()
690 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, in dpp1_dscl_set_scaler_manual_scale()
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| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_transform_v.c | 165 set_reg_field_value(value, data->taps.h_taps - 1, in setup_scaling_configuration()
176 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
560 coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); in dce110_xfmv_set_scaler()
583 data->taps.h_taps, in dce110_xfmv_set_scaler()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 657 plane->composition.scaler_info.plane0.h_taps = 1; in populate_dml21_dummy_plane_cfg()
659 plane->composition.scaler_info.plane1.h_taps = 0; in populate_dml21_dummy_plane_cfg()
775 if (!scaler_data->taps.h_taps) { in populate_dml21_plane_config_from_plane_state()
785 if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) || in populate_dml21_plane_config_from_plane_state()
808 if (!scaler_data->taps.h_taps) { in populate_dml21_plane_config_from_plane_state()
809 plane->composition.scaler_info.plane0.h_taps = 1; in populate_dml21_plane_config_from_plane_state()
810 plane->composition.scaler_info.plane1.h_taps = 1; in populate_dml21_plane_config_from_plane_state()
812 plane->composition.scaler_info.plane0.h_taps = scaler_data->taps.h_taps; in populate_dml21_plane_config_from_plane_state()
813 plane->composition.scaler_info.plane1.h_taps = scaler_data->taps.h_taps_c; in populate_dml21_plane_config_from_plane_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| A D | dcn401_dpp_dscl.c | 307 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp401_dscl_set_scl_filter()
318 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp401_dscl_set_scl_filter()
320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp401_dscl_set_scl_filter()
352 dpp, scl_data->taps.h_taps, in dpp401_dscl_set_scl_filter()
1044 dpp, scl_data->taps.h_taps, in dpp401_dscl_program_isharp()
1072 uint32_t h_num_taps = scl_data->taps.h_taps - 1; in dpp401_dscl_set_scaler_manual_scale()
1110 h_num_taps = scl_data->dscl_prog_data.taps.h_taps; in dpp401_dscl_set_scaler_manual_scale()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_debug.c | 87 plane_state->scaling_quality.h_taps, in pre_surface_trace()
291 update->scaling_info->scaling_quality.h_taps, in update_surface_trace()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| A D | dcn30_dpp.c | 438 if (in_taps->h_taps == 0) { in dpp3_get_optimal_number_of_taps()
440 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
442 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
444 scl_data->taps.h_taps = in_taps->h_taps; in dpp3_get_optimal_number_of_taps()
507 scl_data->taps.h_taps = 1; in dpp3_get_optimal_number_of_taps()
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| /linux/drivers/gpu/drm/amd/display/dc/basics/ |
| A D | dce_calcs.c | 380 data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); in calculate_bandwidth()
381 data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); in calculate_bandwidth()
434 data->h_taps[i] = bw_int_to_fixed(1); in calculate_bandwidth()
524 if (bw_mtn(data->hsr[i], data->h_taps[i])) { in calculate_bandwidth()
528 …sr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixe… in calculate_bandwidth()
1704 …data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_t… in calculate_bandwidth()
2828 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2884 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2931 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2983 …data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_t… in populate_initial_data()
[all …]
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| A D | calcs_logger.h | 430 DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i])); in print_bw_calcs_data()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dwb_scl.c | 728 uint32_t h_taps_luma = num_taps.h_taps; in dwb_program_horz_scalar()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | dce_calcs.h | 396 struct bw_fixed h_taps[maximum_number_of_surfaces]; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_translation_helper.c | 1062 if (!scaler_data->taps.h_taps) { in populate_dml_plane_cfg_from_plane_state()
1066 out->HTaps[location] = scaler_data->taps.h_taps; in populate_dml_plane_cfg_from_plane_state()
1222 out->WritebackHTaps[location] = wb_info->dwb_params.scaler_taps.h_taps > 0 ? in populate_dml_writeback_cfg_from_stream_state()
1223 wb_info->dwb_params.scaler_taps.h_taps : 1; in populate_dml_writeback_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared.c | 839 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps != 1.0 in dml2_core_shared_mode_support()
844 …].composition.scaler_info.plane0.h_taps < 1.0 || display_cfg->plane_descriptors[k].composition.sca… in dml2_core_shared_mode_support()
845 ….composition.scaler_info.plane0.h_taps > 1.0 && (display_cfg->plane_descriptors[k].composition.sca… in dml2_core_shared_mode_support()
852 …k].composition.scaler_info.plane1.h_taps < 1 || display_cfg->plane_descriptors[k].composition.scal… in dml2_core_shared_mode_support()
853 …k].composition.scaler_info.plane1.h_taps > 1 && display_cfg->plane_descriptors[k].composition.scal… in dml2_core_shared_mode_support()
976 …scaling_info.h_taps > 2.0 && ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].s… in dml2_core_shared_mode_support()
995 display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps, in dml2_core_shared_mode_support()
996 display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps, in dml2_core_shared_mode_support()
1356 …->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.h_taps, in dml2_core_shared_mode_support()
9961 display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps, in dml2_core_shared_mode_programming()
[all …]
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| A D | dml2_core_dcn4_calcs.c | 7113 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps != 1.0 in dml_core_mode_support()
7118 …].composition.scaler_info.plane0.h_taps < 1.0 || display_cfg->plane_descriptors[k].composition.sca… in dml_core_mode_support()
7119 ….composition.scaler_info.plane0.h_taps > 1.0 && (display_cfg->plane_descriptors[k].composition.sca… in dml_core_mode_support()
7126 …k].composition.scaler_info.plane1.h_taps < 1 || display_cfg->plane_descriptors[k].composition.scal… in dml_core_mode_support()
7127 …k].composition.scaler_info.plane1.h_taps > 1 && display_cfg->plane_descriptors[k].composition.scal… in dml_core_mode_support()
7237 …scaling_info.h_taps > 2.0 && ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].s… in dml_core_mode_support()
7256 display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps, in dml_core_mode_support()
7257 display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_taps, in dml_core_mode_support()
7674 …->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.h_taps, in dml_core_mode_support()
10130 display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps, in dml_core_mode_programming()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | dcn30_fpu.c | 295 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; in dcn30_fpu_populate_dml_writeback_from_context()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
1012 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; in dcn_validate_bandwidth()
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