Searched refs:hart (Results 1 – 17 of 17) sorted by relevance
| /linux/arch/riscv/kernel/ |
| A D | smpboot.c | 73 unsigned long hart; in acpi_parse_rintc() local
90 hart = processor->hart_id; in acpi_parse_rintc()
91 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
96 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
107 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc()
124 unsigned long hart; in of_parse_and_init_cpus() local
130 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus()
134 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus()
142 cpuid, hart); in of_parse_and_init_cpus()
146 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
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| A D | cpu.c | 34 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
35 if (*hart == ~0UL) { in riscv_of_processor_hartid()
40 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
59 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid()
60 if (*hart == ~0UL) { in riscv_early_of_processor_hartid()
66 pr_info("CPU with hartid=%lu is not available\n", *hart); in riscv_early_of_processor_hartid()
74 pr_warn("CPU with hartid=%lu does not support rv32i", *hart); in riscv_early_of_processor_hartid()
79 pr_warn("CPU with hartid=%lu does not support rv64i", *hart); in riscv_early_of_processor_hartid()
89 pr_warn("CPU with hartid=%lu does not support ima", *hart); in riscv_early_of_processor_hartid()
98 *hart); in riscv_early_of_processor_hartid()
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| /linux/Documentation/translations/zh_CN/arch/riscv/ |
| A D | boot.rst | 70 - ``RISCV_BOOT_SPINWAIT``：固件在内核中释放所有的hart，一个hart赢
71 得抽奖并执行早期启动代码，而其他的hart则停在那里等待初始化完成。这种
73 - ``有序启动``：固件只释放一个将执行初始化阶段的hart，然后使用SBI HSM
74 扩展启动所有其他的hart。有序启动方法是启动RISC-V内核的首选启动方法，
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| /linux/Documentation/arch/riscv/ |
| A D | cmodx.rst | 14 applications. At any point the scheduler may migrate a task onto a new hart. If
16 storage with fence.i, the icache on the new hart will no longer be clean. This
17 is due to the behavior of fence.i only affecting the hart that it is called on.
18 Thus, the hart that the task has been migrated to may not have synchronized
29 when the memory map being used by a hart changes. If the prctl() context caused
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| A D | uabi.rst | 45 "isa" and "hart isa" lines in /proc/cpuinfo
50 "hart isa" line, in contrast, describes the set of extensions recognized by the
51 kernel on the particular hart being described, even if those extensions may not
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| A D | boot.rst | 68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
72 - ``Ordered booting``: the firmware releases only one hart that will execute the
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| /linux/Documentation/devicetree/bindings/riscv/ |
| A D | cpus.yaml | 18 hart: A hardware execution context, which contains all the state
62 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart.
68 this hart. These values originate from the RISC-V Privileged
81 The hart ID of this CPU node.
114 by this hart (see ./idle-states.yaml).
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| A D | extensions.yaml | 18 This document defines properties that indicate whether a hart supports a
37 supported by the hart. These are documented in the RISC-V
56 The base ISA implemented by this hart, as described by the 20191213
65 description: Extensions supported by the hart.
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| A D | sifive,plic-1.0.0.yaml | 14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
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| A D | riscv,cpu-intc.yaml | 13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
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| A D | riscv,imsics.yaml | 101 riscv,hart-index-bits:
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| /linux/tools/perf/pmu-events/arch/riscv/ |
| A D | mapfile.csv | 6 # MARCHID base microarchitecture of the hart
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| /linux/arch/riscv/kvm/ |
| A D | aia_device.c | 240 u32 hart = 0, group = 0; in aia_imsic_hart_index() local
243 hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) & in aia_imsic_hart_index()
249 return (group << aia->nr_hart_bits) | hart; in aia_imsic_hart_index()
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| /linux/arch/riscv/ |
| A D | Kconfig | 630 which allow a hart to enter a low-power state or to trap to the
872 Since spinwait is incompatible with sparse hart IDs, it requires
873 NR_CPUS be large enough to contain the physical hart ID of the first
874 hart to enter Linux.
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| /linux/Documentation/devicetree/bindings/iio/addac/ |
| A D | adi,ad74115.yaml | 188 adi,dac-hart-slew:
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| /linux/Documentation/devicetree/bindings/cpu/ |
| A D | idle-states.yaml | 57 RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
60 The platform specific suspend (or idle) states of a hart can be either
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| /linux/drivers/clocksource/ |
| A D | Kconfig | 650 This enables the per-hart timer built into all RISC-V systems, which
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