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Searched refs:hsync_end_x (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/mdp4/
A Dmdp4_dsi_encoder.c36 uint32_t hsync_start_x, hsync_end_x; in mdp4_dsi_encoder_mode_set() local
52 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dsi_encoder_mode_set()
66 MDP4_DSI_DISPLAY_HCTRL_END(hsync_end_x)); in mdp4_dsi_encoder_mode_set()
A Dmdp4_dtv_encoder.c36 uint32_t hsync_start_x, hsync_end_x; in mdp4_dtv_encoder_mode_set() local
56 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_dtv_encoder_mode_set()
70 MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x)); in mdp4_dtv_encoder_mode_set()
A Dmdp4_lcdc_encoder.c210 uint32_t hsync_start_x, hsync_end_x; in mdp4_lcdc_encoder_mode_set() local
230 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp4_lcdc_encoder_mode_set()
244 MDP4_LCDC_DISPLAY_HCTRL_END(hsync_end_x)); in mdp4_lcdc_encoder_mode_set()
/linux/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_encoder.c30 uint32_t hsync_start_x, hsync_end_x; in mdp5_vid_encoder_mode_set() local
74 hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1; in mdp5_vid_encoder_mode_set()
100 MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x)); in mdp5_vid_encoder_mode_set()
/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_hw_intf.c107 u32 hsync_start_x, hsync_end_x; in dpu_hw_intf_setup_timing_engine() local
136 hsync_end_x = hsync_period - p->h_front_porch - 1; in dpu_hw_intf_setup_timing_engine()
165 display_hctl = (hsync_end_x << 16) | hsync_start_x; in dpu_hw_intf_setup_timing_engine()
/linux/drivers/gpu/drm/msm/dp/
A Ddp_catalog.c1010 u32 hsync_start_x, hsync_end_x; in dp_catalog_panel_tpg_enable() local
1029 hsync_end_x = hsync_period - (drm_mode->hsync_start - in dp_catalog_panel_tpg_enable()
1036 display_hctl = (hsync_end_x << 16) | hsync_start_x; in dp_catalog_panel_tpg_enable()

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