Searched refs:hw_intf (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| A D | dpu_encoder_phys_vid.c | 20 (e) && (e)->hw_intf ? \
26 (e) && (e)->hw_intf ? \
247 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f); in programmable_fetch_config()
309 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, in dpu_encoder_phys_vid_setup_timing_engine()
597 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); in dpu_encoder_phys_vid_disable()
620 if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status) in dpu_encoder_phys_vid_disable()
657 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1); in dpu_encoder_phys_vid_handle_post_kickoff()
698 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) in dpu_encoder_phys_vid_get_line_count()
701 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); in dpu_encoder_phys_vid_get_line_count()
716 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status) in dpu_encoder_phys_vid_get_frame_count()
[all …]
|
| A D | dpu_encoder_phys_cmd.c | 71 phys_enc->hw_intf, in _dpu_encoder_phys_cmd_update_intf_cfg()
80 phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg); in _dpu_encoder_phys_cmd_update_intf_cfg()
355 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, in dpu_encoder_phys_cmd_tearcheck_config()
408 phys_enc->hw_intf->ops.enable_tearcheck(phys_enc->hw_intf, &tc_cfg); in dpu_encoder_phys_cmd_tearcheck_config()
485 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.connect_external_te) in _dpu_encoder_phys_cmd_connect_te()
489 phys_enc->hw_intf->ops.connect_external_te(phys_enc->hw_intf, enable); in _dpu_encoder_phys_cmd_connect_te()
515 hw_intf = phys_enc->hw_intf; in dpu_encoder_phys_cmd_get_line_count()
516 if (!hw_intf || !hw_intf->ops.get_line_count) in dpu_encoder_phys_cmd_get_line_count()
518 return hw_intf->ops.get_line_count(hw_intf); in dpu_encoder_phys_cmd_get_line_count()
544 phys_enc->hw_intf->ops.disable_tearcheck(phys_enc->hw_intf); in dpu_encoder_phys_cmd_disable()
[all …]
|
| A D | dpu_encoder.c | 292 if (phys->hw_intf && phys->hw_intf->ops.setup_misr in dpu_encoder_get_crc_values_cnt()
311 if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) in dpu_encoder_setup_misr()
314 phys->hw_intf->ops.setup_misr(phys->hw_intf); in dpu_encoder_setup_misr()
334 if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) in dpu_encoder_get_crc()
394 phys_enc->hw_intf ? phys_enc->hw_intf->idx - INTF_0 : -1, in dpu_encoder_helper_report_irq_timeout()
787 phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, in _dpu_encoder_update_vsync_source()
1486 ready_phys->hw_intf ? ready_phys->hw_intf->idx : -1, in dpu_encoder_frame_done_callback()
1564 phys->hw_intf ? phys->hw_intf->idx : -1, in _dpu_encoder_trigger_flush()
2155 if (phys_enc->hw_intf) in dpu_encoder_helper_phys_cleanup()
2261 phys->hw_intf ? phys->hw_intf->idx - INTF_0 : -1, in _dpu_encoder_status_show()
[all …]
|
| A D | dpu_rm.h | 31 struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0]; member
107 return rm->hw_intf[intf_idx - INTF_0]; in dpu_rm_get_intf()
|
| A D | dpu_encoder_phys.h | 182 struct dpu_hw_intf *hw_intf; member
265 struct dpu_hw_intf *hw_intf; member
|
| A D | dpu_rm.c | 107 rm->hw_intf[intf->id - INTF_0] = hw; in dpu_rm_init()
|
Completed in 20 milliseconds