Searched refs:idf (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/clk/st/ |
| A D | clkgen-pll.c | 212 u32 idf; member
368 if (!pll->idf) in clk_pll3200c32_get_rate()
369 pll->idf = 1; in clk_pll3200c32_get_rate()
387 idf = CLKGEN_READ(pll, idf); in recalc_stm_pll3200c32()
389 if (idf) in recalc_stm_pll3200c32()
442 pll->idf = params.idf; in set_rate_stm_pll3200c32()
451 CLKGEN_WRITE(pll, idf, pll->idf); in set_rate_stm_pll3200c32()
524 if (!pll->idf) in clk_pll4600c28_get_rate()
543 params.idf = CLKGEN_READ(pll, idf); in recalc_stm_pll4600c28()
601 pll->idf = params.idf; in set_rate_stm_pll4600c28()
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| /linux/drivers/gpu/drm/stm/ |
| A D | dw_mipi_dsi-stm.c | 139 int divisor = idf * odf; in dsi_pll_get_clkout_khz()
150 int *idf, int *ndiv, int *odf) in dsi_pll_get_params() argument
190 *idf = i; in dsi_pll_get_params()
256 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; in dw_mipi_dsi_clk_recalc_rate() local
265 idf = (val & WRPCR_IDF) >> 11; in dw_mipi_dsi_clk_recalc_rate()
266 if (!idf) in dw_mipi_dsi_clk_recalc_rate()
267 idf = 1; in dw_mipi_dsi_clk_recalc_rate()
289 idf = 0; in dw_mipi_dsi_clk_round_rate()
294 &idf, &ndiv, &odf); in dw_mipi_dsi_clk_round_rate()
317 idf = 0; in dw_mipi_dsi_clk_set_rate()
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| /linux/drivers/gpu/drm/sti/ |
| A D | sti_hdmi_tx3g4c28phy.c | 47 uint32_t idf; member
79 u32 val, tmdsck, idf, odf, pllctrl = 0; in sti_hdmi_tx3g4c28phy_start() local
88 idf = plldividers[i].idf; in sti_hdmi_tx3g4c28phy_start()
110 pllctrl |= idf << PLL_CFG_IDF_SHIFT; in sti_hdmi_tx3g4c28phy_start()
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| /linux/drivers/gpu/drm/i915/display/ |
| A D | dvo_ch7xxx.c | 291 u8 tvco, tpcp, tpd, tlpf, idf; in ch7xxx_mode_set() local
313 ch7xxx_readb(dvo, CH7xxx_IDF, &idf); in ch7xxx_mode_set()
315 idf |= CH7xxx_IDF_IBS; in ch7xxx_mode_set()
317 idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); in ch7xxx_mode_set()
319 idf |= CH7xxx_IDF_HSP; in ch7xxx_mode_set()
322 idf |= CH7xxx_IDF_VSP; in ch7xxx_mode_set()
324 ch7xxx_writeb(dvo, CH7xxx_IDF, idf); in ch7xxx_mode_set()
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| /linux/drivers/media/dvb-frontends/ |
| A D | stv0910.c | 789 u32 idf = 1; in set_mclock() local
793 u32 ndiv = (fphi * odf * idf) / quartz; in set_mclock()
840 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf); in set_mclock()
844 fvco = (quartz * 2 * ndiv) / idf; in set_mclock()
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