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Searched refs:inst_idx (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dvcn_v4_0_5.c470 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_5_mc_resume_dpg_mode()
527 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), in vcn_v4_0_5_mc_resume_dpg_mode()
532 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), in vcn_v4_0_5_mc_resume_dpg_mode()
759 int inst_idx, uint8_t indirect) in vcn_v4_0_5_disable_clock_gating_dpg_mode() argument
889 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = in vcn_v4_0_5_start_dpg_mode()
918 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_5_start_dpg_mode()
922 VCN, inst_idx, regUVD_MPC_SET_MUXA0), in vcn_v4_0_5_start_dpg_mode()
929 VCN, inst_idx, regUVD_MPC_SET_MUXB0), in vcn_v4_0_5_start_dpg_mode()
936 VCN, inst_idx, regUVD_MPC_SET_MUX), in vcn_v4_0_5_start_dpg_mode()
955 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_5_start_dpg_mode()
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A Dvcn_v5_0_0.c84 int inst_idx, struct dpg_pause_state *new_state);
432 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), in vcn_v5_0_0_mc_resume_dpg_mode()
486 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), in vcn_v5_0_0_mc_resume_dpg_mode()
634 int inst_idx, uint8_t indirect)
679 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v5_0_0_start_dpg_mode()
717 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v5_0_0_start_dpg_mode()
721 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); in vcn_v5_0_0_start_dpg_mode()
723 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v5_0_0_start_dpg_mode()
733 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); in vcn_v5_0_0_start_dpg_mode()
734 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); in vcn_v5_0_0_start_dpg_mode()
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A Damdgpu_jpeg.h38 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
41 JPEG, GET_INST(JPEG, inst_idx), \
47 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
49 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
56 WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \
65 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
67 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
70 JPEG, GET_INST(JPEG, inst_idx), \
79 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
81 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
[all …]
A Dvcn_v3_0.c577 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v3_0_mc_resume_dpg_mode()
631 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v3_0_mc_resume_dpg_mode()
1003 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v3_0_start_dpg_mode()
1032 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
1036 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), in vcn_v3_0_start_dpg_mode()
1043 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), in vcn_v3_0_start_dpg_mode()
1050 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
1077 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1085 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); in vcn_v3_0_start_dpg_mode()
1087 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v3_0_start_dpg_mode()
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A Dvcn_v4_0.c519 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), in vcn_v4_0_mc_resume_dpg_mode()
573 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), in vcn_v4_0_mc_resume_dpg_mode()
823 int inst_idx, uint8_t indirect) in vcn_v4_0_disable_clock_gating_dpg_mode() argument
940 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
945 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
975 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v4_0_start_dpg_mode()
1003 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_start_dpg_mode()
1007 VCN, inst_idx, regUVD_MPC_SET_MUXA0), in vcn_v4_0_start_dpg_mode()
1014 VCN, inst_idx, regUVD_MPC_SET_MUXB0), in vcn_v4_0_start_dpg_mode()
1021 VCN, inst_idx, regUVD_MPC_SET_MUX), in vcn_v4_0_start_dpg_mode()
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A Damdgpu_vcn.h83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
189 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
192 VCN, GET_INST(VCN, inst_idx), \
198 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
200 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
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A Dvcn_v2_5.c101 int inst_idx, struct dpg_pause_state *new_state);
852 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
857 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
862 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
883 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v2_5_start_dpg_mode()
946 vcn_v2_6_enable_ras(adev, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
963 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); in vcn_v2_5_start_dpg_mode()
965 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v2_5_start_dpg_mode()
997 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
1000 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
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A Dvcn_v4_0_3.c97 int inst_idx, bool indirect);
385 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_mc_resume()
573 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_disable_clock_gating()
661 int inst_idx, uint8_t indirect) in vcn_v4_0_3_disable_clock_gating_dpg_mode() argument
717 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_enable_clock_gating()
769 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_start_dpg_mode()
781 inst_idx, adev->vcn.inst[inst_idx].aid_id); in vcn_v4_0_3_start_dpg_mode()
1903 int inst_idx, bool indirect) in vcn_v4_0_3_enable_ras() argument
1914 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras()
1919 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras()
[all …]
A Djpeg_v5_0_0.c279 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
318 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v5_0_0_start_dpg_mode()
329 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v5_0_0_start_dpg_mode()
330 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; in jpeg_v5_0_0_start_dpg_mode()
344 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_SYS_INT_EN, in jpeg_v5_0_0_start_dpg_mode()
347 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_SYS_INT_EN, in jpeg_v5_0_0_start_dpg_mode()
354 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0); in jpeg_v5_0_0_start_dpg_mode()
361 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v5_0_0_start_dpg_mode()
363 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v5_0_0_start_dpg_mode()
367 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0); in jpeg_v5_0_0_start_dpg_mode()
[all …]
A Djpeg_v4_0_5.c328 int inst_idx, uint8_t indirect) in jpeg_engine_4_0_5_dpg_clock_gating_mode() argument
395 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v4_0_5_start_dpg_mode()
407 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
417 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v4_0_5_start_dpg_mode()
418 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; in jpeg_v4_0_5_start_dpg_mode()
433 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0); in jpeg_v4_0_5_start_dpg_mode()
435 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v4_0_5_start_dpg_mode()
437 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v4_0_5_start_dpg_mode()
439 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v4_0_5_start_dpg_mode()
441 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0); in jpeg_v4_0_5_start_dpg_mode()
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A Damdgpu_jpeg.c333 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_jpeg_psp_update_sram() argument
338 .mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_jpeg_psp_update_sram()
339 .ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_jpeg_psp_update_sram()
340 (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_jpeg_psp_update_sram()
A Dvcn_v1_0.c90 int inst_idx, struct dpg_pause_state *new_state);
1253 int inst_idx, struct dpg_pause_state *new_state) in vcn_v1_0_pause_dpg_mode() argument
1261 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v1_0_pause_dpg_mode()
1263 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1264 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1313 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v1_0_pause_dpg_mode()
1317 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1319 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1320 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1374 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
A Damdgpu_vcn.c1266 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_vcn_psp_update_sram() argument
1271 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : in amdgpu_vcn_psp_update_sram()
1273 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_vcn_psp_update_sram()
1274 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_vcn_psp_update_sram()
1275 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_vcn_psp_update_sram()
A Djpeg_v4_0_3.c422 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_disable_clock_gating() argument
427 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating()
447 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_enable_clock_gating() argument
452 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating()
A Dvcn_v2_0.c98 int inst_idx, struct dpg_pause_state *new_state);
1246 int inst_idx, struct dpg_pause_state *new_state) in vcn_v2_0_pause_dpg_mode() argument
1253 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1255 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1316 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
A Daqua_vanjaram.c71 uint32_t inst_idx, struct amdgpu_ring *ring) in aqua_vanjaram_set_xcp_id() argument
83 inst_mask = 1 << inst_idx; in aqua_vanjaram_set_xcp_id()

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