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Searched refs:intel_de_posting_read (Results 1 – 25 of 31) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
A Dintel_fdi.c497 intel_de_posting_read(dev_priv, reg); in intel_fdi_normal_train()
550 intel_de_posting_read(dev_priv, reg); in ilk_fdi_link_train()
632 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
661 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
712 intel_de_posting_read(dev_priv, reg); in gen6_fdi_link_train()
770 intel_de_posting_read(dev_priv, reg); in ivb_manual_fdi_link_train()
812 intel_de_posting_read(dev_priv, reg); in ivb_manual_fdi_link_train()
1043 intel_de_posting_read(dev_priv, reg); in ilk_fdi_pll_enable()
1048 intel_de_posting_read(dev_priv, reg); in ilk_fdi_pll_enable()
1099 intel_de_posting_read(dev_priv, reg); in ilk_fdi_disable()
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A Dg4x_hdmi.c62 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in intel_hdmi_prepare()
233 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in g4x_hdmi_enable_port()
297 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
299 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
312 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
319 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
321 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
360 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
367 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
398 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); in intel_disable_hdmi()
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A Dg4x_dp.c216 intel_de_posting_read(display, DP_A); in ilk_edp_pll_on()
231 intel_de_posting_read(display, DP_A); in ilk_edp_pll_on()
251 intel_de_posting_read(display, DP_A); in ilk_edp_pll_off()
443 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
447 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
467 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
471 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
628 intel_de_posting_read(display, intel_dp->output_reg); in cpt_set_link_train()
656 intel_de_posting_read(display, intel_dp->output_reg); in g4x_set_link_train()
678 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_enable_port()
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A Dintel_fifo_underrun.c107 intel_de_posting_read(dev_priv, reg); in i9xx_check_fifo_underruns()
127 intel_de_posting_read(dev_priv, reg); in i9xx_set_fifo_underrun_reporting()
160 intel_de_posting_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
249 intel_de_posting_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
A Dintel_pps.c153 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
156 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
773 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
845 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
976 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
992 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1004 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1052 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_off_unlocked()
1096 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_on()
1117 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_off()
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A Dintel_pch_refclk.c616 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
635 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
646 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
660 intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
A Dintel_hdmi.c308 intel_de_posting_read(display, reg); in ibx_write_infoframe()
386 intel_de_posting_read(display, reg); in cpt_write_infoframe()
458 intel_de_posting_read(display, reg); in vlv_write_infoframe()
895 intel_de_posting_read(display, reg); in g4x_set_infoframes()
915 intel_de_posting_read(display, reg); in g4x_set_infoframes()
1069 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1090 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1126 intel_de_posting_read(display, reg); in cpt_set_infoframes()
1139 intel_de_posting_read(display, reg); in cpt_set_infoframes()
1197 intel_de_posting_read(display, reg); in vlv_set_infoframes()
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A Dintel_pipe_crc.c613 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); in intel_crtc_set_crc_source()
648 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); in intel_crtc_enable_pipe_crc()
663 intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); in intel_crtc_disable_pipe_crc()
A Dintel_dkl_phy.c111 intel_de_posting_read(i915, DKL_REG_MMIO(reg)); in intel_dkl_phy_posting_read()
A Dintel_vga.c46 intel_de_posting_read(dev_priv, vga_reg); in intel_vga_disable()
A Dintel_dpll_mgr.c574 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_enable()
583 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_enable()
593 intel_de_posting_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_disable()
696 intel_de_posting_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
707 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_enable()
717 intel_de_posting_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
733 intel_de_posting_read(i915, SPLL_CTL); in hsw_ddi_spll_disable()
1371 intel_de_posting_read(i915, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1386 intel_de_posting_read(i915, regs[id].cfgcr1); in skl_ddi_pll_enable()
1413 intel_de_posting_read(i915, regs[id].ctl); in skl_ddi_pll_disable()
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A Dintel_backlight.c502 intel_de_posting_read(i915, BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
539 intel_de_posting_read(i915, BLC_PWM_CPU_CTL2); in pch_enable_backlight()
553 intel_de_posting_read(i915, BLC_PWM_PCH_CTL1); in pch_enable_backlight()
583 intel_de_posting_read(i915, BLC_PWM_CTL); in i9xx_enable_backlight()
627 intel_de_posting_read(i915, BLC_PWM_CTL2); in i965_enable_backlight()
660 intel_de_posting_read(i915, VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
709 intel_de_posting_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller)); in bxt_enable_backlight()
740 intel_de_posting_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller)); in cnp_enable_backlight()
A Dintel_dvo.c195 intel_de_posting_read(i915, DVO(port)); in intel_disable_dvo()
212 intel_de_posting_read(i915, DVO(port)); in intel_enable_dvo()
A Dintel_dpll.c1852 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
1870 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_enable_pll()
1999 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in _vlv_enable_pll()
2029 intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); in vlv_enable_pll()
2198 intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); in chv_enable_pll()
2253 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in vlv_disable_pll()
2271 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in chv_disable_pll()
2297 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i9xx_disable_pll()
A Dintel_de.h76 #define intel_de_posting_read(p,...) __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__) macro
A Dintel_crt.c505 intel_de_posting_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
733 intel_de_posting_read(dev_priv, in intel_crt_load_detect()
977 intel_de_posting_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
A Dhsw_ips.c83 intel_de_posting_read(i915, IPS_CTL); in hsw_ips_disable()
A Dintel_display_power.c1048 intel_de_posting_read(dev_priv, reg); in gen9_dbuf_slice_set()
1243 intel_de_posting_read(dev_priv, D_COMP_BDW); in hsw_write_dcomp()
1277 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1293 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1320 intel_de_posting_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
A Dintel_lvds.c326 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_enable_lvds()
349 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_disable_lvds()
A Dintel_gmbus.c288 intel_de_posting_read(i915, bus->gpio_reg); in set_clock()
305 intel_de_posting_read(i915, bus->gpio_reg); in set_data()
A Dicl_dsi.c365 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
371 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
378 intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8)); in gen11_dsi_program_esc_clk_div()
673 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
A Dintel_ddi.c1484 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in hsw_set_signal_levels()
2332 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_disable_fec()
3326 intel_de_posting_read(dev_priv, reg); in intel_enable_ddi_hdmi()
3579 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in mtl_ddi_prepare_link_retrain()
3596 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in mtl_ddi_prepare_link_retrain()
3624 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3639 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); in intel_ddi_prepare_link_retrain()
3647 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_prepare_link_retrain()
A Dvlv_dsi_pll.c547 intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()
A Dintel_sdvo.c222 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
229 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
246 intel_de_posting_read(dev_priv, GEN3_SDVOB); in intel_sdvo_write_sdvox()
249 intel_de_posting_read(dev_priv, GEN3_SDVOC); in intel_sdvo_write_sdvox()
A Dintel_display.c476 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in intel_enable_transcoder()
2985 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in i9xx_set_pipeconf()
3216 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in ilk_set_pipeconf()
3246 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in hsw_set_transconf()
8316 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i830_enable_pipe()
8329 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i830_enable_pipe()
8334 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); in i830_enable_pipe()
8358 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); in i830_disable_pipe()
8363 intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); in i830_disable_pipe()

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