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Searched refs:intel_de_read (Results 1 – 25 of 63) sorted by relevance

123

/linux/drivers/gpu/drm/i915/display/
A Dintel_fdi.c39 cur_state = intel_de_read(dev_priv, in assert_fdi_tx()
475 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
486 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
528 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
532 intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
537 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
545 temp = intel_de_read(dev_priv, reg); in ilk_fdi_link_train()
627 temp = intel_de_read(dev_priv, reg); in gen6_fdi_link_train()
637 temp = intel_de_read(dev_priv, reg); in gen6_fdi_link_train()
651 temp = intel_de_read(dev_priv, reg); in gen6_fdi_link_train()
[all …]
A Dintel_pch_display.c107 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
117 u32 val = intel_de_read(dev_priv, hdmi_reg); in ibx_sanitize_pch_hdmi_port()
136 u32 val = intel_de_read(dev_priv, dp_reg); in ibx_sanitize_pch_dp_port()
260 val = intel_de_read(dev_priv, reg); in ilk_enable_pch_transcoder()
273 val = intel_de_read(dev_priv, reg); in ilk_enable_pch_transcoder()
380 temp = intel_de_read(dev_priv, PCH_DPLL_SEL); in ilk_pch_enable()
421 temp = intel_de_read(dev_priv, reg); in ilk_pch_enable()
505 tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); in ilk_pch_get_config()
519 tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); in ilk_pch_get_config()
561 pipeconf_val = intel_de_read(dev_priv, in lpt_enable_pch_transcoder()
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A Dintel_combo_phy.c59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
95 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
153 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
155 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
157 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
336 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
350 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
356 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
A Dintel_crt.c89 val = intel_de_read(dev_priv, adpa_reg); in intel_crt_port_enabled()
126 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
510 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
561 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
711 save_bclrpat = intel_de_read(dev_priv, in intel_crt_load_detect()
713 save_vtotal = intel_de_read(dev_priv, in intel_crt_load_detect()
715 vblank = intel_de_read(dev_priv, in intel_crt_load_detect()
728 u32 transconf = intel_de_read(dev_priv, in intel_crt_load_detect()
754 u32 vsync = intel_de_read(dev_priv, in intel_crt_load_detect()
973 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
[all …]
A Dintel_display_power_well.c589 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_enabled()
599 val |= intel_de_read(dev_priv, regs->bios); in hsw_power_well_enabled()
610 intel_de_read(dev_priv, DC_STATE_EN) & in assert_can_enable_dc9()
614 intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & in assert_can_enable_dc9()
634 intel_de_read(dev_priv, DC_STATE_EN) & in assert_can_disable_dc9()
662 v = intel_de_read(dev_priv, DC_STATE_EN); in gen9_write_dc_state()
757 val = intel_de_read(dev_priv, DC_STATE_EN); in gen9_set_dc_state()
807 (intel_de_read(dev_priv, DC_STATE_EN) & in assert_can_enable_dc5()
834 (intel_de_read(dev_priv, UTIL_PIN_CTL) & in assert_can_enable_dc6()
839 (intel_de_read(dev_priv, DC_STATE_EN) & in assert_can_enable_dc6()
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A Dintel_backlight.c249 tmp = intel_de_read(i915, BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
349 tmp = intel_de_read(i915, BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
565 ctl = intel_de_read(i915, BLC_PWM_CTL); in i9xx_enable_backlight()
606 ctl2 = intel_de_read(i915, BLC_PWM_CTL2); in i965_enable_backlight()
675 val = intel_de_read(i915, UTIL_PIN_CTL); in bxt_enable_backlight()
1308 ctl = intel_de_read(i915, BLC_PWM_CTL); in i9xx_setup_backlight()
1350 ctl2 = intel_de_read(i915, BLC_PWM_CTL2); in i965_setup_backlight()
1354 ctl = intel_de_read(i915, BLC_PWM_CTL); in i965_setup_backlight()
1418 pwm_ctl = intel_de_read(i915, in bxt_setup_backlight()
1423 val = intel_de_read(i915, UTIL_PIN_CTL); in bxt_setup_backlight()
[all …]
A Dintel_pps.c301 u32 port_sel = intel_de_read(display, in vlv_initial_pps_pipe()
623 intel_de_read(display, pp_stat_reg), in wait_panel_status()
624 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
631 intel_de_read(display, pp_stat_reg), in wait_panel_status()
632 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
778 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_on_unlocked()
779 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_on_unlocked()
852 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_off_sync_unlocked()
1595 intel_de_read(display, regs.pp_on), in pps_init_registers()
1596 intel_de_read(display, regs.pp_off), in pps_init_registers()
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A Dintel_fifo_underrun.c102 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
129 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
152 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
183 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
240 u32 serr_int = intel_de_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
273 if (old && intel_de_read(dev_priv, SERR_INT) & in cpt_set_fifo_underrun_reporting()
422 underruns = intel_de_read(dev_priv, in intel_cpu_fifo_underrun_irq_handler()
A Dintel_dpll_mgr.c536 val = intel_de_read(i915, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
757 val = intel_de_read(i915, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
778 val = intel_de_read(i915, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1439 val = intel_de_read(i915, regs[id].ctl); in skl_ddi_pll_get_hw_state()
1443 val = intel_de_read(i915, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1478 val = intel_de_read(i915, regs[id].ctl); in skl_ddi_dpll0_get_hw_state()
1482 val = intel_de_read(i915, DPLL_CTRL1); in skl_ddi_dpll0_get_hw_state()
2219 hw_state->pcsdw12 = intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
2225 intel_de_read(i915, in bxt_ddi_pll_get_hw_state()
3553 val = intel_de_read(i915, enable_reg); in mg_pll_get_hw_state()
[all …]
A Dicl_dsi.c184 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
296 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); in configure_dual_link_mode()
453 tmp = intel_de_read(dev_priv, in gen11_dsi_config_phy_lanes_sequence()
608 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_gate_clocks()
624 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_ungate_clocks()
640 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_is_clock_enabled()
661 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
801 tmp = intel_de_read(dev_priv, in gen11_dsi_configure_transcoder()
1093 tmp = intel_de_read(dev_priv, UTIL_PIN_CTL); in gen11_dsi_config_util_pin()
1326 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); in gen11_dsi_deconfigure_trancoder()
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A Dintel_tc.c305 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in lnl_tc_port_get_max_lane_count()
501 pch_isr = intel_de_read(i915, SDEISR); in icl_tc_phy_hpd_live_status()
738 val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1)); in tgl_tc_phy_init()
785 cpu_isr = intel_de_read(i915, GEN11_DE_HPD_ISR); in adlp_tc_phy_hpd_live_status()
786 pch_isr = intel_de_read(i915, SDEISR); in adlp_tc_phy_hpd_live_status()
815 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in adlp_tc_phy_is_ready()
848 val = intel_de_read(i915, DDI_BUF_CTL(port)); in adlp_tc_phy_is_owned()
973 pica_isr = intel_de_read(i915, PICAINTERRUPT_ISR); in xelpdp_tc_phy_hpd_live_status()
974 pch_isr = intel_de_read(i915, SDEISR); in xelpdp_tc_phy_hpd_live_status()
1025 val = intel_de_read(i915, reg); in __xelpdp_tc_phy_enable_tcss_power()
[all …]
A Dintel_pch_refclk.c17 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
23 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
234 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) in lpt_get_iclkip()
397 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in spll_uses_pch_ssc()
398 u32 ctl = intel_de_read(dev_priv, SPLL_CTL); in spll_uses_pch_ssc()
417 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in wrpll_uses_pch_ssc()
418 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); in wrpll_uses_pch_ssc()
534 temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id)); in ilk_init_pch_refclk()
555 val = intel_de_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
A Dvlv_dsi.c122 u32 val = intel_de_read(display, reg); in read_data()
638 temp = intel_de_read(display, port_ctrl); in intel_dsi_port_enable()
975 enabled = intel_de_read(display, in intel_dsi_get_hw_state()
980 u32 tmp = intel_de_read(display, in intel_dsi_get_hw_state()
1055 intel_de_read(display, in bxt_dsi_get_pipe_config()
1058 intel_de_read(display, in bxt_dsi_get_pipe_config()
1061 intel_de_read(display, in bxt_dsi_get_pipe_config()
1065 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1072 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1334 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); in intel_dsi_prepare()
[all …]
A Dintel_ddi.c649 ctl = intel_de_read(dev_priv, in intel_ddi_disable_transcoder_func()
728 tmp = intel_de_read(dev_priv, in intel_ddi_connector_get_hw_state()
792 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
833 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
1932 tmp = intel_de_read(i915, DPLL_CTRL2); in skl_ddi_get_pll()
3316 val = intel_de_read(dev_priv, reg); in intel_enable_ddi_hdmi()
3768 u32 ctl2 = intel_de_read(dev_priv, in bdw_transcoder_master_readout()
3776 u32 ctl = intel_de_read(dev_priv, in bdw_transcoder_master_readout()
3833 temp = intel_de_read(dev_priv, in intel_ddi_read_func_ctl()
3905 intel_de_read(dev_priv, in intel_ddi_read_func_ctl()
[all …]
A Dintel_lvds.c94 val = intel_de_read(i915, lvds_reg); in intel_lvds_port_enabled()
133 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
151 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); in intel_lvds_get_config()
164 pps->powerdown_on_reset = intel_de_read(dev_priv, in intel_lvds_pps_get_hw_state()
167 val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)); in intel_lvds_pps_get_hw_state()
172 val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0)); in intel_lvds_pps_get_hw_state()
176 val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0)); in intel_lvds_pps_get_hw_state()
213 val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0)); in intel_lvds_pps_init_hw()
816 val = intel_de_read(i915, lvds_encoder->reg); in compute_is_dual_link_lvds()
868 lvds = intel_de_read(i915, lvds_reg); in intel_lvds_init()
A Dintel_display_power.c1159 u32 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_assert_cdclk()
1189 intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1230 return intel_de_read(dev_priv, D_COMP_HSW); in hsw_read_dcomp()
1232 return intel_de_read(dev_priv, D_COMP_BDW); in hsw_read_dcomp()
1262 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1268 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & in hsw_disable_lcpll()
1272 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_disable_lcpll()
1305 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
1328 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_restore_lcpll()
1338 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & in hsw_restore_lcpll()
[all …]
A Dintel_vrr.c331 return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; in intel_vrr_is_push_sent()
387 trans_vrr_ctl = intel_de_read(display, in intel_vrr_get_config()
412 crtc_state->vrr.flipline = intel_de_read(display, in intel_vrr_get_config()
414 crtc_state->vrr.vmax = intel_de_read(display, in intel_vrr_get_config()
416 crtc_state->vrr.vmin = intel_de_read(display, in intel_vrr_get_config()
425 intel_de_read(display, in intel_vrr_get_config()
A Dg4x_dp.c185 bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE; in assert_edp_pll()
262 u32 val = intel_de_read(display, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
287 val = intel_de_read(display, dp_reg); in g4x_dp_port_enabled()
355 tmp = intel_de_read(display, intel_dp->output_reg); in intel_dp_get_config()
360 u32 trans_dp = intel_de_read(display, in intel_dp_get_config()
428 (intel_de_read(display, intel_dp->output_reg) & in intel_dp_link_down()
689 u32 dp_reg = intel_de_read(display, intel_dp->output_reg); in intel_enable_dp()
1201 return intel_de_read(display, SDEISR) & bit; in ibx_digital_port_connected()
1224 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit; in g4x_digital_port_connected()
1232 return intel_de_read(display, DEISR) & bit; in ilk_digital_port_connected()
[all …]
A Dintel_vga.c34 if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE) in intel_vga_disable()
53 if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) { in intel_vga_redisable_power_on()
A Dintel_tv.c918 u32 tmp = intel_de_read(display, TV_CTL); in intel_tv_get_hw_state()
1107 tv_ctl = intel_de_read(display, TV_CTL); in intel_tv_get_config()
1108 hctl1 = intel_de_read(display, TV_H_CTL_1); in intel_tv_get_config()
1109 hctl3 = intel_de_read(display, TV_H_CTL_3); in intel_tv_get_config()
1110 vctl1 = intel_de_read(display, TV_V_CTL_1); in intel_tv_get_config()
1111 vctl2 = intel_de_read(display, TV_V_CTL_2); in intel_tv_get_config()
1146 tmp = intel_de_read(display, TV_WIN_POS); in intel_tv_get_config()
1150 tmp = intel_de_read(display, TV_WIN_SIZE); in intel_tv_get_config()
1455 tv_ctl = intel_de_read(display, TV_CTL); in intel_tv_pre_enable()
1640 tv_dac = intel_de_read(display, TV_DAC); in intel_tv_detect_type()
[all …]
A Dintel_overlay.c332 tmp = intel_de_read(dev_priv, DOVSTA); in intel_overlay_continue()
954 tmp = intel_de_read(dev_priv, in update_pfit_vscale_ratio()
957 tmp = intel_de_read(dev_priv, in update_pfit_vscale_ratio()
1301 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); in intel_overlay_attrs_ioctl()
1302 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); in intel_overlay_attrs_ioctl()
1303 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); in intel_overlay_attrs_ioctl()
1304 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); in intel_overlay_attrs_ioctl()
1305 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); in intel_overlay_attrs_ioctl()
1306 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); in intel_overlay_attrs_ioctl()
1480 error->dovsta = intel_de_read(dev_priv, DOVSTA); in intel_overlay_capture_error_state()
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A Dintel_hdmi.c281 u32 val = intel_de_read(display, reg); in ibx_write_infoframe()
334 u32 val = intel_de_read(display, reg); in ibx_infoframes_enabled()
356 u32 val = intel_de_read(display, reg); in cpt_write_infoframe()
430 u32 val = intel_de_read(display, reg); in vlv_write_infoframe()
475 *data++ = intel_de_read(display, in vlv_read_infoframe()
551 *data++ = intel_de_read(display, in hsw_read_infoframe()
559 u32 val = intel_de_read(display, in hsw_infoframes_enabled()
867 u32 val = intel_de_read(display, reg); in g4x_set_infoframes()
1054 u32 val = intel_de_read(display, reg); in ibx_set_infoframes()
1112 u32 val = intel_de_read(display, reg); in cpt_set_infoframes()
[all …]
A Dvlv_dsi_pll.c270 val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
284 val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
358 config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
372 temp = intel_de_read(display, MIPI_CTRL(display, port)); in vlv_dsi_reset_clocks()
439 tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
579 tmp = intel_de_read(display, BXT_MIPI_CLOCK_CTL); in bxt_dsi_reset_clocks()
A Dintel_display.c334 u32 val = intel_de_read(dev_priv, in assert_transcoder()
2828 return intel_de_read(dev_priv, in intel_pipe_is_interlaced()
2849 tmp = intel_de_read(dev_priv, in intel_get_transcoder_timings()
2865 tmp = intel_de_read(dev_priv, in intel_get_transcoder_timings()
2883 intel_de_read(dev_priv, in intel_get_transcoder_timings()
3067 tmp = intel_de_read(dev_priv, in i9xx_get_pipe_config()
3445 tmp = intel_de_read(dev_priv, in ilk_get_pipe_config()
3531 tmp = intel_de_read(dev_priv, in transcoder_ddi_func_is_enabled()
3755 tmp = intel_de_read(dev_priv, in hsw_get_transcoder_state()
3762 tmp = intel_de_read(dev_priv, in hsw_get_transcoder_state()
[all …]
/linux/drivers/gpu/drm/i915/
A Di915_suspend.c43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, in intel_save_swf()
45 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, in intel_save_swf()
49 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, in intel_save_swf()
53 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, in intel_save_swf()
57 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, in intel_save_swf()
59 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, in intel_save_swf()
63 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, in intel_save_swf()
109 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, in i915_save_display()

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