| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr_vbios_smu.c | 153 khz_to_mhz_ceil(requested_dispclk_khz)); in rn_vbios_smu_set_dispclk()
162 ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz)); in rn_vbios_smu_set_dispclk()
174 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rn_vbios_smu_set_dprefclk()
191 khz_to_mhz_ceil(requested_dcfclk_khz)); in rn_vbios_smu_set_hard_min_dcfclk()
206 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in rn_vbios_smu_set_min_deep_sleep_dcfclk()
216 khz_to_mhz_ceil(requested_phyclk_khz)); in rn_vbios_smu_set_phyclk()
226 khz_to_mhz_ceil(requested_dpp_khz)); in rn_vbios_smu_set_dppclk()
228 ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz)); in rn_vbios_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | dcn301_smu.c | 155 khz_to_mhz_ceil(requested_dispclk_khz)); in dcn301_smu_set_dispclk()
169 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn301_smu_set_dprefclk()
185 khz_to_mhz_ceil(requested_dcfclk_khz)); in dcn301_smu_set_hard_min_dcfclk()
199 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in dcn301_smu_set_min_deep_sleep_dcfclk()
213 khz_to_mhz_ceil(requested_dpp_khz)); in dcn301_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_smu.c | 186 khz_to_mhz_ceil(requested_dispclk_khz)); in dcn314_smu_set_dispclk()
201 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn314_smu_set_dprefclk()
221 khz_to_mhz_ceil(requested_dcfclk_khz)); in dcn314_smu_set_hard_min_dcfclk()
239 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in dcn314_smu_set_min_deep_sleep_dcfclk()
254 khz_to_mhz_ceil(requested_dpp_khz)); in dcn314_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_smu.c | 167 khz_to_mhz_ceil(requested_dispclk_khz)); in dcn31_smu_set_dispclk()
182 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn31_smu_set_dprefclk()
202 khz_to_mhz_ceil(requested_dcfclk_khz)); in dcn31_smu_set_hard_min_dcfclk()
220 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in dcn31_smu_set_min_deep_sleep_dcfclk()
235 khz_to_mhz_ceil(requested_dpp_khz)); in dcn31_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| A D | rv1_clk_mgr.c | 264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
266 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
284 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
285 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
286 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
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| A D | rv1_clk_mgr_vbios_smu.c | 135 khz_to_mhz_ceil(requested_dispclk_khz)); in rv1_vbios_smu_set_dispclk()
153 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rv1_vbios_smu_set_dprefclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_smu.c | 172 khz_to_mhz_ceil(requested_dispclk_khz)); in dcn316_smu_set_dispclk()
190 khz_to_mhz_ceil(requested_dcfclk_khz)); in dcn316_smu_set_hard_min_dcfclk()
208 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in dcn316_smu_set_min_deep_sleep_dcfclk()
223 khz_to_mhz_ceil(requested_dpp_khz)); in dcn316_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_smu.c | 198 khz_to_mhz_ceil(requested_dispclk_khz)); in dcn315_smu_set_dispclk()
216 khz_to_mhz_ceil(requested_dcfclk_khz)); in dcn315_smu_set_hard_min_dcfclk()
234 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in dcn315_smu_set_min_deep_sleep_dcfclk()
249 khz_to_mhz_ceil(requested_dpp_khz)); in dcn315_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_smu.c | 204 khz_to_mhz_ceil(requested_dispclk_khz)); in dcn35_smu_set_dispclk()
220 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn35_smu_set_dprefclk()
237 khz_to_mhz_ceil(requested_dcfclk_khz)); in dcn35_smu_set_hard_min_dcfclk()
254 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); in dcn35_smu_set_min_deep_sleep_dcfclk()
271 khz_to_mhz_ceil(requested_dpp_khz)); in dcn35_smu_set_dppclk()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.c | 236 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_k… in dcn3_update_clocks()
241 …dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_slee… in dcn3_update_clocks()
283 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz… in dcn3_update_clocks()
290 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_kh… in dcn3_update_clocks()
296 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_… in dcn3_update_clocks()
365 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); in dcn3_set_hard_min_memclk()
484 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_kh… in dcn30_notify_link_rate_change()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| A D | dcn401_clk_mgr.c | 287 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) in dcn401_init_clocks()
289 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); in dcn401_init_clocks()
295 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) in dcn401_init_clocks()
297 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); in dcn401_init_clocks()
953 int active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz); in dcn401_build_update_bandwidth_clocks_sequence()
954 int active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz); in dcn401_build_update_bandwidth_clocks_sequence()
956 int idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz); in dcn401_build_update_bandwidth_clocks_sequence()
1099 active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz); in dcn401_build_update_bandwidth_clocks_sequence()
1108 idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz); in dcn401_build_update_bandwidth_clocks_sequence()
1119 active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz); in dcn401_build_update_bandwidth_clocks_sequence()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
272 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_… in dcn2_update_clocks()
278 …pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.socclk_khz… in dcn2_update_clocks()
293 …pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)… in dcn2_update_clocks()
318 …pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks… in dcn2_update_clocks()
513 …pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.… in dcn2_notify_link_rate_change()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| A D | dcn32_clk_mgr.c | 239 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) in dcn32_init_clocks()
241 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); in dcn32_init_clocks()
250 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) in dcn32_init_clocks()
252 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); in dcn32_init_clocks()
683 …dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_kh… in dcn32_update_clocks()
689 …dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_slee… in dcn32_update_clocks()
758 …max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramcl… in dcn32_update_clocks()
760 …dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz… in dcn32_update_clocks()
806 …dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); in dcn32_update_clocks()
1004 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); in dcn32_set_hard_min_memclk()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr_internal.h | 393 static inline int khz_to_mhz_ceil(int khz) in khz_to_mhz_ceil() function
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