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Searched refs:lane_count (Results 1 – 25 of 83) sorted by relevance

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/linux/drivers/gpu/drm/tests/
A Ddrm_dp_mst_helper_test.c73 int lane_count; member
94 .lane_count = 4,
99 .lane_count = 2,
104 .lane_count = 1,
109 .lane_count = 4,
114 .lane_count = 2,
119 .lane_count = 1,
124 .lane_count = 4,
129 .lane_count = 2,
134 .lane_count = 1,
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/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_dp_capability.c463 switch (lane_count) { in reduce_lane_count()
512 switch (lane_count) { in increase_lane_count()
582 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && in decide_fallback_link_setting_max_bw_policy()
592 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || in decide_fallback_link_setting_max_bw_policy()
610 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count; in decide_fallback_link_setting_max_bw_policy()
654 cur->lane_count = reduce_lane_count(cur->lane_count); in decide_fallback_link_setting()
664 cur->lane_count = reduce_lane_count(cur->lane_count); in decide_fallback_link_setting()
673 cur->lane_count = max->lane_count; in decide_fallback_link_setting()
689 cur->lane_count = max->lane_count; in decide_fallback_link_setting()
893 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { in decide_edp_link_settings_with_dsc()
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A Dlink_dp_training_fixed_vs_pe_retimer.c75 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings() argument
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
254 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence()
295 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence()
325 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local
376 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
414 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence()
455 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence() local
483 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence()
533 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence()
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A Dlink_dp_training_8b_10b.c103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
164 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
232 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence()
271 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
284 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
337 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
343 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
344 dp_is_symbol_locked(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
A Dlink_dp_training_dpia.c295 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local
400 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent()
406 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent()
461 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local
504 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent()
590 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local
684 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_non_transparent()
689 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent()
734 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_transparent() local
767 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_transparent()
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A Dlink_dp_training.c172 lt_settings->link_settings.lane_count, in dp_log_training_result()
467 (uint32_t)(lt_settings->link_settings.lane_count); in dp_is_max_vs_reached()
1096 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
1142 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1152 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1177 link_training_setting->link_settings.lane_count); in dpcd_set_lane_settings()
1403 enum dc_lane_count lane_count = in perform_post_lt_adj_req_sequence() local
1404 lt_settings->link_settings.lane_count; in perform_post_lt_adj_req_sequence()
1615 (cur_link_settings.lane_count <= LANE_COUNT_ONE); in perform_link_training_with_retries()
1670 link->verified_link_cap.lane_count = link->cur_link_settings.lane_count; in perform_link_training_with_retries()
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A Dlink_dp_irq_handler.c59 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status()
65 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status()
283 pipes[i]->link_config.dp_link_settings.lane_count = in dp_handle_link_loss()
284 link->verified_link_cap.lane_count; in dp_handle_link_loss()
375 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || in dp_should_allow_hpd_rx_irq()
/linux/drivers/gpu/drm/i915/display/
A Dintel_dp_link_training.c1183 int lane_count; in reduce_link_params_in_bw_order() local
1248 int lane_count; in reduce_link_params_in_rate_lane_order() local
1250 lane_count = crtc_state->lane_count; in reduce_link_params_in_rate_lane_order()
1253 lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); in reduce_link_params_in_rate_lane_order()
1257 if (lane_count < 0) in reduce_link_params_in_rate_lane_order()
1826 int lane_count; in parse_lane_count() local
1836 lane_count = 0; in parse_lane_count()
1842 switch (lane_count) { in parse_lane_count()
1866 int lane_count; in i915_dp_force_lane_count_write() local
1870 if (lane_count < 0) in i915_dp_force_lane_count_write()
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A Dintel_dpio_phy.c600 switch (lane_count) { in bxt_dpio_phy_calc_lane_lat_optim_mask()
608 MISSING_CASE(lane_count); in bxt_dpio_phy_calc_lane_lat_optim_mask()
737 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
750 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
803 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
829 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
846 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
913 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable()
956 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
965 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable()
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A Dintel_dp.h56 int link_rate, int lane_count);
110 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
111 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
143 u32 link_clock, u32 lane_count,
160 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
162 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
A Dvlv_dsi.c57 8 * 100), lane_count); in txbyteclkhs()
64 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1023 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1075 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1128 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1130 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1132 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1224 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings() local
1247 hactive = txbyteclkhs(hactive, bpp, lane_count, in set_dsi_timings()
1250 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings()
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A Dintel_combo_phy.c261 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
268 switch (lane_count) { in intel_combo_phy_power_up_lanes()
279 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
286 switch (lane_count) { in intel_combo_phy_power_up_lanes()
296 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
A Dvlv_dsi_pll.c48 int lane_count) in dsi_clk_from_pclk() argument
55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk()
183 intel_dsi->lane_count); in vlv_dsi_pll_compute()
349 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk()
488 intel_dsi->lane_count); in bxt_dsi_pll_compute()
A Dintel_dp_mst.c106 overhead = drm_dp_bw_overhead(crtc_state->lane_count, in intel_dp_mst_bw_overhead()
129 intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, in intel_dp_mst_compute_m_n()
190 crtc_state->lane_count = limits->max_lane_count; in intel_dp_mst_find_vcpi_slots_for_bpp()
202 crtc_state->lane_count); in intel_dp_mst_find_vcpi_slots_for_bpp()
271 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); in intel_dp_mst_find_vcpi_slots_for_bpp()
1138 int link_rate, int lane_count) in intel_mst_probed_link_params_valid() argument
1141 intel_dp->link.mst_probed_lane_count == lane_count; in intel_mst_probed_link_params_valid()
1145 int link_rate, int lane_count) in intel_mst_set_probed_link_params() argument
1148 intel_dp->link.mst_probed_lane_count = lane_count; in intel_mst_set_probed_link_params()
1161 crtc_state->port_clock, crtc_state->lane_count); in intel_mst_reprobe_topology()
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A Dintel_dp.c380 int lane_count; in intel_dp_max_lane_count() local
387 switch (lane_count) { in intel_dp_max_lane_count()
391 return lane_count; in intel_dp_max_lane_count()
393 MISSING_CASE(lane_count); in intel_dp_max_lane_count()
774 u8 lane_count) in intel_dp_link_params_valid() argument
785 if (lane_count == 0 || in intel_dp_link_params_valid()
1727 lane_count); in intel_dp_compute_link_config_wide()
1731 pipe_config->lane_count = lane_count; in intel_dp_compute_link_config_wide()
1918 lane_count <<= 1) { in dsc_compute_link_config()
1925 pipe_config->lane_count = lane_count; in dsc_compute_link_config()
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/linux/drivers/gpu/drm/bridge/analogix/
A Danalogix_dp_core.c229 int lane, lane_count, retval; in analogix_dp_link_start() local
231 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
288 lane_count); in analogix_dp_link_start()
317 int lane_count) in analogix_dp_channel_eq_ok() argument
365 int lane, lane_count; in analogix_dp_get_adjust_training_lane() local
368 lane_count = dp->link_train.lane_count; in analogix_dp_get_adjust_training_lane()
388 int lane, lane_count, retval; in analogix_dp_process_clock_recovery() local
394 lane_count = dp->link_train.lane_count; in analogix_dp_process_clock_recovery()
454 int lane_count, retval; in analogix_dp_process_equalizer_training() local
460 lane_count = dp->link_train.lane_count; in analogix_dp_process_equalizer_training()
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/linux/drivers/gpu/drm/msm/dp/
A Ddp_panel.h88 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
90 return (lane_count == 1 || in is_lane_count_valid()
91 lane_count == 2 || in is_lane_count_valid()
92 lane_count == 4); in is_lane_count_valid()
/linux/drivers/gpu/drm/gma500/
A Dcdv_intel_dp.c262 uint8_t lane_count; member
897 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
910 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
916 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
990 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1007 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
1010 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
1054 switch (intel_dp->lane_count) { in cdv_intel_dp_mode_set()
1387 intel_dp->lane_count); in cdv_intel_dplink_set_level()
1389 if (ret != intel_dp->lane_count) { in cdv_intel_dplink_set_level()
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/linux/drivers/gpu/drm/bridge/
A Dparade-ps8622.c54 u32 lane_count; member
184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
490 &ps8622->lane_count)) { in ps8622_probe()
491 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
492 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
495 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
A Dite-it6505.c429 u8 lane_count; member
822 switch (it6505->lane_count) { in it6505_lane_termination_on()
834 switch (it6505->lane_count) { in it6505_lane_termination_on()
1490 it6505->lane_count); in it6505_parse_link_capabilities()
1491 it6505->lane_count = min_t(int, it6505->lane_count, in it6505_parse_link_capabilities()
1564 (it6505->lane_count - 1) << 1); in it6505_lane_count_setup()
1581 it6505->lane_count, in it6505_link_training_setup()
1622 values[1] = it6505->lane_count; in it6505_drm_dp_link_configure()
1645 u8 lane_count) in it6505_check_max_voltage_swing_reached() argument
1649 for (i = 0; i < lane_count; i++) { in it6505_check_max_voltage_swing_reached()
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn31/
A Ddcn31_dio_link_encoder.c475 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output()
522 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output()
658 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
680 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
/linux/drivers/gpu/drm/mediatek/
A Dmtk_dp.c74 int lane_count; member
1234 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1241 .lanes = lane_count, in mtk_dp_phy_configure()
1427 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init()
1460 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank()
1498 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu()
1824 lane_count = lane_count / 2; in mtk_dp_training()
1826 if (lane_count == 0) in mtk_dp_training()
1849 if (lane_count == 0) in mtk_dp_training()
1851 lane_count /= 2; in mtk_dp_training()
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/linux/drivers/gpu/drm/display/
A Ddrm_dp_helper.c90 int lane_count) in drm_dp_channel_eq_ok() argument
100 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
110 int lane_count) in drm_dp_clock_recovery_ok() argument
115 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
166 int lane_count) in drm_dp_128b132b_lane_channel_eq_done() argument
175 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_channel_eq_done()
186 int lane_count) in drm_dp_128b132b_lane_symbol_locked() argument
191 for (lane = 0; lane < lane_count; lane++) { in drm_dp_128b132b_lane_symbol_locked()
4150 int align = is_mst ? 4 / lane_count : 1; in drm_dp_link_symbol_cycles()
4191 int drm_dp_bw_overhead(int lane_count, int hactive, in drm_dp_bw_overhead() argument
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/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
A Dlink_hwss_hpo_fixed_vs_pe_retimer_dp.c107 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
114 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
201 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
/linux/include/drm/display/
A Ddrm_dp_helper.h37 int lane_count);
39 int lane_count);
62 int lane_count);
64 int lane_count);
869 int drm_dp_bw_overhead(int lane_count, int hactive,

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