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Searched refs:mask1 (Results 1 – 25 of 74) sorted by relevance

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/linux/tools/testing/selftests/bpf/progs/
A Dcpumask_success.c102 mask1 = create_cpumask(); in create_cpumask_set()
103 if (!mask1) in create_cpumask_set()
130 *out1 = mask1; in create_cpumask_set()
260 mask1 = create_cpumask(); in BPF_PROG()
261 if (!mask1) in BPF_PROG()
276 if (mask1) in BPF_PROG()
600 if (!mask1) in _global_mask_array_rcu()
604 if (*mask1) { in _global_mask_array_rcu()
622 if (!*mask0 || !*mask1 || *mask0 == *mask1) { in _global_mask_array_rcu()
760 if (!mask1 || !mask2) in BPF_PROG()
[all …]
/linux/sound/pci/ice1712/
A Dwm8776.c135 .mask1 = WM8776_DACVOL_MASK,
145 .mask1 = WM8776_DAC_PL_LL,
153 .mask1 = WM8776_DAC_DZCEN,
161 .mask1 = WM8776_HPVOL_MASK,
171 .mask1 = WM8776_PWR_HPPD,
179 .mask1 = WM8776_VOL_HPZCEN,
187 .mask1 = WM8776_OUTMUX_AUX,
199 .mask1 = WM8776_DAC_IZD,
214 .mask1 = WM8776_DAC2_DEEMPH,
232 .mask1 = WM8776_ADC_MUTEL,
[all …]
A Dwm8766.c36 .mask1 = WM8766_VOL_MASK,
47 .mask1 = WM8766_VOL_MASK,
58 .mask1 = WM8766_VOL_MASK,
67 .mask1 = WM8766_DAC2_MUTE1,
74 .mask1 = WM8766_DAC2_MUTE2,
81 .mask1 = WM8766_DAC2_MUTE3,
106 .mask1 = WM8766_DAC2_DEEMP1,
112 .mask1 = WM8766_DAC2_DEEMP2,
118 .mask1 = WM8766_DAC2_DEEMP3,
124 .mask1 = WM8766_DAC_IZD,
[all …]
/linux/drivers/ras/amd/atl/
A Dsystem.c56 static void df3_get_masks_shifts(u32 mask0, u32 mask1) in df3_get_masks_shifts() argument
61 df_cfg.node_id_shift = FIELD_GET(DF3_NODE_ID_SHIFT, mask1); in df3_get_masks_shifts()
62 df_cfg.socket_id_shift = FIELD_GET(DF3_SOCKET_ID_SHIFT, mask1); in df3_get_masks_shifts()
63 df_cfg.socket_id_mask = FIELD_GET(DF3_SOCKET_ID_MASK, mask1); in df3_get_masks_shifts()
64 df_cfg.die_id_mask = FIELD_GET(DF3_DIE_ID_MASK, mask1); in df3_get_masks_shifts()
72 df_cfg.node_id_shift = FIELD_GET(DF3_NODE_ID_SHIFT, mask1); in df3p5_get_masks_shifts()
73 df_cfg.socket_id_shift = FIELD_GET(DF4_SOCKET_ID_SHIFT, mask1); in df3p5_get_masks_shifts()
81 df3p5_get_masks_shifts(mask0, mask1, mask2); in df4_get_masks_shifts()
96 u32 mask0, mask1, mask2; in df4_get_fabric_id_mask_registers() local
103 if (df_indirect_read_broadcast(0, 4, 0x1B4, &mask1)) in df4_get_fabric_id_mask_registers()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc_helper.c108 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in set_reg_field_values() argument
116 field_value1, mask1, shift1); in set_reg_field_values()
223 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_update_ex() argument
251 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_set_ex() argument
286 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get2() argument
296 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get3() argument
308 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get4() argument
322 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get5() argument
338 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get6() argument
539 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_indirect_reg_update_ex() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dmub/src/
A Ddmub_reg.c45 uint32_t mask1, uint32_t field_value1, in set_reg_field_values() argument
52 set_reg_field_value_masks(field_value_mask, field_value1, mask1, in set_reg_field_values()
73 uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_update() argument
80 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_update()
90 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_set() argument
96 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_set()
/linux/fs/orangefs/
A Dorangefs-debugfs.c63 __u64 mask1; member
456 c_mask.mask1, in orangefs_debug_write()
543 (unsigned long long *)&(cdm_array[i].mask1), in orangefs_prepare_cdm_array()
755 if ((mask->mask1 & cdm_array[index].mask1) || in do_c_string()
799 if ((c_mask->mask1 == cdm_array[client_all_index].mask1) && in check_amalgam_keyword()
806 if ((c_mask->mask1 == cdm_array[client_verbose_index].mask1) && in check_amalgam_keyword()
875 (**sane_mask).mask1 = (**sane_mask).mask1 | cdm_array[i].mask1; in do_c_mask()
900 client_debug_mask.mask1 = mask2_info.mask1_value; in orangefs_debugfs_new_client_mask()
906 (unsigned long long)client_debug_mask.mask1, in orangefs_debugfs_new_client_mask()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/
A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
227 reg1 ## __ ## mask1 ## _MASK,\
229 reg1 ## __ ## mask1 ## _MASK,\
230 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
232 reg1 ## __ ## mask1 ## _MASK,\
234 reg1 ## __ ## mask1 ## _MASK,\
235 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/
A Dirq_service_dcn401.c189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
203 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
206 reg1 ## __ ## mask1 ## _MASK,\
208 reg1 ## __ ## mask1 ## _MASK,\
209 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
216 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
219 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
227 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
230 reg1 ## __ ## mask1 ## _MASK,\
232 reg1 ## __ ## mask1 ## _MASK,\
233 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
237 reg1 ## __ ## mask1 ## _MASK,\
239 reg1 ## __ ## mask1 ## _MASK,\
240 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
216 reg1 ## __ ## mask1 ## _MASK,\
218 reg1 ## __ ## mask1 ## _MASK,\
219 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
225 reg1 ## __ ## mask1 ## _MASK,\
227 reg1 ## __ ## mask1 ## _MASK,\
228 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/
A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
226 reg1 ## __ ## mask1 ## _MASK,\
228 reg1 ## __ ## mask1 ## _MASK,\
229 ~reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
221 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
224 reg1 ## __ ## mask1 ## _MASK,\
226 reg1 ## __ ## mask1 ## _MASK,\
228 ~reg1 ## __ ## mask1 ## _MASK, \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
193 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \
200 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
203 reg1 ## __ ## mask1 ## _MASK,\
205 reg1 ## __ ## mask1 ## _MASK,\
207 ~reg1 ## __ ## mask1 ## _MASK, \
/linux/arch/alpha/kernel/
A Dsys_rawhide.c102 unsigned int mask, mask1, hose; in rawhide_mask_and_ack_irq() local
111 mask1 = 1 << irq; in rawhide_mask_and_ack_irq()
112 mask = ~mask1 | hose_irq_masks[hose]; in rawhide_mask_and_ack_irq()
121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
/linux/arch/mips/sgi-ip27/
A Dip27-nmi.c127 u64 mask0, mask1, pend0, pend1; in nmi_dump_hub_irq() local
131 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); in nmi_dump_hub_irq()
134 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); in nmi_dump_hub_irq()
140 pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1); in nmi_dump_hub_irq()
/linux/drivers/soc/fsl/qe/
A Dgpio.c241 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated() local
260 if (sregs->cpdata & mask1) in qe_pin_set_dedicated()
261 qe_gc->cpdata |= mask1; in qe_pin_set_dedicated()
263 qe_gc->cpdata &= ~mask1; in qe_pin_set_dedicated()
266 qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1); in qe_pin_set_dedicated()
/linux/include/linux/
A Dcpumask.h345 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
346 for_each_and_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
363 #define for_each_cpu_andnot(cpu, mask1, mask2) \ argument
364 for_each_andnot_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
380 #define for_each_cpu_or(cpu, mask1, mask2) \ argument
381 for_each_or_bit(cpu, cpumask_bits(mask1), cpumask_bits(mask2), small_cpumask_bits)
422 unsigned int cpumask_any_and_but(const struct cpumask *mask1, in cpumask_any_and_but() argument
429 i = cpumask_first_and(mask1, mask2); in cpumask_any_and_but()
433 return cpumask_next_and(cpu, mask1, mask2); in cpumask_any_and_but()
857 #define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) argument
/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
106 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
109 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/pcmcia/
A Dtcic.c241 u_int mask1; in irq_scan() local
252 mask1 = 0; in irq_scan()
256 mask1 |= (1 << i); in irq_scan()
258 if ((mask1 & (1 << i)) && (try_irq(i) != 0)) { in irq_scan()
259 mask1 ^= (1 << i); in irq_scan()
263 if (mask1) { in irq_scan()
270 mask1 |= (1 << i); in irq_scan()
278 if (mask1 & (1<<i)) in irq_scan()
279 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i); in irq_scan()
282 return mask1; in irq_scan()
/linux/drivers/net/hamradio/
A Dhdlcdrv.c159 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
177 for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00, in hdlcdrv_receiver()
180 i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1, in hdlcdrv_receiver()
182 if ((s->hdlcrx.bitstream & mask1) == mask1) in hdlcdrv_receiver()
255 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
330 mask1 = 0x1f000; in hdlcdrv_transmitter()
334 for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1, in hdlcdrv_transmitter()
336 if ((s->hdlctx.bitstream & mask1) != mask1) in hdlcdrv_transmitter()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c138 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
140 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
142 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
143 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

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