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Searched refs:mask_sh (Results 1 – 25 of 130) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn31/
A Ddcn31_hubp.h33 #define HUBP_MASK_SH_LIST_DCN31(mask_sh)\ argument
41 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
42 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
46 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
48 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
49 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\
50 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
53 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
54 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
177 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
A Ddcn30_hubp.h37 #define HUBP_MASK_SH_LIST_DCN30_BASE(mask_sh)\ argument
38 HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\
47 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh)
50 #define HUBP_MASK_SH_LIST_DCN30(mask_sh)\ argument
58 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
63 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
64 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
65 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
69 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
193 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.h10 #define OPTC_COMMON_MASK_SH_LIST_DCN401(mask_sh)\ argument
13 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
14 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
26 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
32 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
39 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
43 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
75 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
99 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
100 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.h34 #define SE_COMMON_MASK_SH_LIST_DCN32(mask_sh)\ argument
50 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
71 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
72 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
78 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
80 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
82 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
83 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
104 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
117 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.h31 #define OPTC_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\ argument
47 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
53 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
60 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
64 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
96 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
120 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
121 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
122 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
134 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
A Ddcn401_dccg.h34 #define DCCG_MASK_SH_LIST_DCN401(mask_sh) \ argument
39 DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\
40 DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\
41 DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\
42 DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\
94 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
96 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
98 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
100 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
116 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn401/
A Ddcn401_dio_stream_encoder.h34 #define SE_COMMON_MASK_SH_LIST_DCN401(mask_sh)\ argument
51 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
60 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
62 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\
73 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
74 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
80 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
82 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
84 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
85 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
[all …]
A Ddcn401_dio_link_encoder.h44 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
45 LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
52 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
53 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
54 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
55 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
56 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
57 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
58 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
59 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
A Ddcn401_hubp.h44 #define HUBP_MASK_SH_LIST_DCN401(mask_sh)\ argument
52 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
53 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
57 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
59 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
60 HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\
61 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
64 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
65 HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
164 HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
A Ddcn35_dccg.h47 #define DCCG_MASK_SH_LIST_DCN35(mask_sh) \ argument
52 DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\
53 DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\
54 DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\
55 DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\
78 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\
79 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\
80 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\
81 DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\
132 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
A Ddcn401_dsc.h16 #define DSC_REG_LIST_SH_MASK_DCN401(mask_sh)\ argument
17 DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \
21 DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
75 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
76 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
77 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
79 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
80 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
81 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
82 DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
A Ddcn401_dpp.h35 #define DPP_REG_LIST_SH_MASK_DCN401_COMMON(mask_sh)\ argument
37 TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\
38 TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\
39 TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\
40 TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\
41 TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\
104 TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
109 TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
110 TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
173 TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_mmhubbub.h135 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \ argument
230 SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
267 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN30(mask_sh) \ argument
289 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
296 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
304 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
311 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
319 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
326 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
334 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
A Ddcn20_dpp.h186 #define TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh)\ argument
209 #define TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh)\ argument
210 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
368 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE, mask_sh), \
369 TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_SIZE, mask_sh), \
371 TF_SF(CM0_CM_3DLUT_DATA, CM_3DLUT_DATA0, mask_sh), \
545 #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\ argument
546 TF_REG_LIST_SH_MASK_DCN(mask_sh), \
547 TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
548 TF_REG_LIST_SH_MASK_DCN20_UPDATED(mask_sh), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_link_encoder.h32 #define LINK_ENCODER_MASK_SH_LIST_DCN35(mask_sh) \ argument
46 LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
53 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
54 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
55 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
56 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
57 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
58 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
59 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
60 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
[all …]
A Ddcn35_dio_stream_encoder.h114 #define SE_COMMON_MASK_SH_LIST_DCN35(mask_sh)\ argument
130 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
151 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
152 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
158 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
160 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
162 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
163 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
184 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
197 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.h114 #define DCN30_VTOTAL_REGS_SF(mask_sh) argument
132 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
138 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
145 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
149 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
168 DCN30_VTOTAL_REGS_SF(mask_sh)\
183 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
212 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
213 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
214 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
A Ddcn314_dccg.h80 #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \ argument
89 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
90 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
91 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
92 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
137 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
139 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
141 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
143 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
170 #define DCCG_MASK_SH_LIST_DCN314(mask_sh) \ argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.h120 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
126 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
133 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
137 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
169 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
193 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
194 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
206 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
208 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_link_encoder.h35 #define UNIPHY_MASK_SH_LIST(mask_sh)\ argument
43 #define DPCS_MASK_SH_LIST(mask_sh)\ argument
153 #define DPCS_DCN2_MASK_SH_LIST(mask_sh)\ argument
154 DPCS_MASK_SH_LIST(mask_sh),\
175 #define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\ argument
176 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
177 LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
180 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_LANE0EN, mask_sh),\
184 LE_SF(DIG0_DIG_LANE_ENABLE, DIG_CLK_EN, mask_sh),\
185 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
A Ddcn30_dio_stream_encoder.h115 #define SE_COMMON_MASK_SH_LIST_DCN30(mask_sh)\ argument
130 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
149 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
150 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
151 SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
157 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
159 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
162 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
198 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
211 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
A Ddcn32_dccg.h34 #define DCCG_MASK_SH_LIST_DCN32(mask_sh) \ argument
57 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\
58 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\
59 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\
60 DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\
72 DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
105 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\
106 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\
108 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\
110 DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/
A Ddcn401_hubbub.h35 #define HUBBUB_MASK_SH_LIST_DCN4_01(mask_sh)\ argument
67 HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
68 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
69 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
70 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
71 HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
80 HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\
81 HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
83 HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
85 HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.h119 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
125 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
132 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
136 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
168 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
191 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
192 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
193 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
205 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
207 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/
A Ddcn32_hubbub.h31 #define HUBBUB_MASK_SH_LIST_DCN32(mask_sh)\ argument
47 HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
50 HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
51 HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
52 HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
53 HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
54 HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
68 HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
70 HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
72 HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\
[all …]

Completed in 81 milliseconds

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