| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 372 unsigned int meta_req_height; in get_meta_and_pte_attr() local
493 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
506 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
507 + meta_req_height; in get_meta_and_pte_attr()
508 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
554 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_rq_dlg_calc_20v2.c | 372 unsigned int meta_req_height; in get_meta_and_pte_attr() local
493 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
506 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
507 + meta_req_height; in get_meta_and_pte_attr()
508 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
554 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 362 unsigned int meta_req_height; in get_meta_and_pte_attr() local
487 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
500 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
501 + meta_req_height; in get_meta_and_pte_attr()
502 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
551 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_mode_vba_21.c | 438 unsigned int meta_req_height[],
1966 &locals->meta_req_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2530 locals->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4682 &locals->meta_req_height[k], in dml21_ModeSupportAndSystemConfigurationFull()
5859 unsigned int meta_req_height[], in CalculateMetaAndPTETimes()
5936 - meta_req_height[k]; in CalculateMetaAndPTETimes()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 318 unsigned int meta_req_height = 0; in get_meta_and_pte_attr() local
466 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
479 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
480 + meta_req_height; in get_meta_and_pte_attr()
481 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
527 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_mode_vba_30.c | 459 int meta_req_height[],
2277 &v->meta_req_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2881 v->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5684 int meta_req_height[], in CalculateMetaAndPTETimes() argument
5754 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; in CalculateMetaAndPTETimes()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 341 unsigned int meta_req_height; in get_meta_and_pte_attr() local
483 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
495 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height; in get_meta_and_pte_attr()
496 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
528 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_mode_vba_31.c | 423 int meta_req_height[],
2399 &v->meta_req_height[k],
3033 v->meta_req_height,
6046 int meta_req_height[], argument
6116 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | dml1_display_rq_dlg_calc.c | 584 unsigned int meta_req_height; in get_surf_rq_param() local
727 meta_req_height = 1 << log2_meta_req_height; in get_surf_rq_param()
741 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_surf_rq_param()
742 + meta_req_height; in get_surf_rq_param()
743 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_surf_rq_param()
784 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_surf_rq_param()
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| A D | display_mode_vba.h | 831 unsigned int meta_req_height[DC__NUM_DPP__MAX]; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 429 unsigned int meta_req_height; in get_meta_and_pte_attr() local
571 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
583 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height; in get_meta_and_pte_attr()
584 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
616 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_mode_vba_314.c | 432 int meta_req_height[],
2418 &v->meta_req_height[k],
3052 v->meta_req_height,
6141 int meta_req_height[], argument
6211 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 399 unsigned int meta_req_height[],
914 unsigned int meta_req_height[],
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| A D | display_mode_vba_util_32.c | 1936 unsigned int meta_req_height[], in dml32_CalculateVMRowAndSwath()
2126 &meta_req_height[k], in dml32_CalculateVMRowAndSwath()
4894 unsigned int meta_req_height[], in dml32_CalculateMetaAndPTETimes()
4964 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; in dml32_CalculateMetaAndPTETimes()
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| A D | display_mode_vba_32.c | 495 v->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1311 v->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 630 unsigned int meta_req_height[DML2_MAX_PLANES]; member
1486 unsigned int *meta_req_height; member
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| A D | dml2_core_shared.c | 9224 meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_height[k]; in CalculateMetaAndPTETimes()
10266 CalculateVMRowAndSwath_params->meta_req_height_luma = mode_lib->mp.meta_req_height; in dml2_core_shared_mode_programming()
11178 CalculateMetaAndPTETimes_params->meta_req_height = mode_lib->mp.meta_req_height; in dml2_core_shared_mode_programming()
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| A D | dml2_core_dcn4_calcs.c | 9381 meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_height[k]; in CalculateMetaAndPTETimes()
10395 CalculateVMRowAndSwath_params->meta_req_height_luma = mode_lib->mp.meta_req_height; in dml_core_mode_programming()
11358 CalculateMetaAndPTETimes_params->meta_req_height = mode_lib->mp.meta_req_height; in dml_core_mode_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core_structs.h | 1008 dml_uint_t meta_req_height[__DML_NUM_PLANES__]; member
1365 dml_uint_t *meta_req_height; member
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| A D | display_mode_core.c | 517 dml_uint_t meta_req_height[],
3443 dml_uint_t meta_req_height[], in CalculateMetaAndPTETimes()
3514 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; in CalculateMetaAndPTETimes()
5190 &p->meta_req_height[k], in CalculateVMRowAndSwath()
7712 CalculateVMRowAndSwath_params->meta_req_height = s->dummy_integer_array[6]; in dml_core_mode_support()
8724 CalculateVMRowAndSwath_params->meta_req_height = locals->meta_req_height; in dml_core_mode_programming()
9552 locals->meta_req_height, in dml_core_mode_programming()
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