| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 371 unsigned int meta_req_width; in get_meta_and_pte_attr() local
492 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
501 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
502 + meta_req_width; in get_meta_and_pte_attr()
503 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
552 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_rq_dlg_calc_20v2.c | 371 unsigned int meta_req_width; in get_meta_and_pte_attr() local
492 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
501 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
502 + meta_req_width; in get_meta_and_pte_attr()
503 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
552 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 361 unsigned int meta_req_width; in get_meta_and_pte_attr() local
486 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
495 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
496 + meta_req_width; in get_meta_and_pte_attr()
497 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
549 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_mode_vba_21.c | 437 unsigned int meta_req_width[],
1965 &locals->meta_req_width[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2529 locals->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4681 &locals->meta_req_width[k], in dml21_ModeSupportAndSystemConfigurationFull()
5858 unsigned int meta_req_width[], in CalculateMetaAndPTETimes() argument
5933 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 317 unsigned int meta_req_width = 0; in get_meta_and_pte_attr() local
465 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
474 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
475 + meta_req_width; in get_meta_and_pte_attr()
476 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
525 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_mode_vba_30.c | 457 int meta_req_width[],
2276 &v->meta_req_width[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2879 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5682 int meta_req_width[], in CalculateMetaAndPTETimes() argument
5752 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 340 unsigned int meta_req_width; in get_meta_and_pte_attr() local
482 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
491 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width; in get_meta_and_pte_attr()
492 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
526 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_mode_vba_31.c | 421 int meta_req_width[],
2398 &v->meta_req_width[k],
3031 v->meta_req_width,
6044 int meta_req_width[], argument
6114 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | dml1_display_rq_dlg_calc.c | 583 unsigned int meta_req_width; in get_surf_rq_param() local
726 meta_req_width = 1 << log2_meta_req_width; in get_surf_rq_param()
736 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_surf_rq_param()
737 + meta_req_width; in get_surf_rq_param()
738 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_surf_rq_param()
782 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_surf_rq_param()
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| A D | display_mode_vba.h | 832 unsigned int meta_req_width[DC__NUM_DPP__MAX]; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 428 unsigned int meta_req_width; in get_meta_and_pte_attr() local
570 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
579 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width; in get_meta_and_pte_attr()
580 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
614 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_mode_vba_314.c | 430 int meta_req_width[],
2417 &v->meta_req_width[k],
3050 v->meta_req_width,
6139 int meta_req_width[], argument
6209 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 397 unsigned int meta_req_width[],
912 unsigned int meta_req_width[],
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| A D | display_mode_vba_util_32.c | 1934 unsigned int meta_req_width[], in dml32_CalculateVMRowAndSwath()
2125 &meta_req_width[k], in dml32_CalculateVMRowAndSwath()
4892 unsigned int meta_req_width[], in dml32_CalculateMetaAndPTETimes() argument
4962 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in dml32_CalculateMetaAndPTETimes()
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| A D | display_mode_vba_32.c | 493 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1309 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 629 unsigned int meta_req_width[DML2_MAX_PLANES]; member
1484 unsigned int *meta_req_width; member
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| A D | dml2_core_shared.c | 9222 meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_width[k]; in CalculateMetaAndPTETimes()
10265 CalculateVMRowAndSwath_params->meta_req_width_luma = mode_lib->mp.meta_req_width; in dml2_core_shared_mode_programming()
11176 CalculateMetaAndPTETimes_params->meta_req_width = mode_lib->mp.meta_req_width; in dml2_core_shared_mode_programming()
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| A D | dml2_core_dcn4_calcs.c | 9379 meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_width[k]; in CalculateMetaAndPTETimes()
10394 CalculateVMRowAndSwath_params->meta_req_width_luma = mode_lib->mp.meta_req_width; in dml_core_mode_programming()
11356 CalculateMetaAndPTETimes_params->meta_req_width = mode_lib->mp.meta_req_width; in dml_core_mode_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core_structs.h | 1007 dml_uint_t meta_req_width[__DML_NUM_PLANES__]; member
1363 dml_uint_t *meta_req_width; member
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| A D | display_mode_core.c | 515 dml_uint_t meta_req_width[],
3441 dml_uint_t meta_req_width[], in CalculateMetaAndPTETimes() argument
3512 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()
5189 &p->meta_req_width[k], in CalculateVMRowAndSwath()
7710 CalculateVMRowAndSwath_params->meta_req_width = s->dummy_integer_array[4]; in dml_core_mode_support()
8722 CalculateVMRowAndSwath_params->meta_req_width = locals->meta_req_width; in dml_core_mode_programming()
9550 locals->meta_req_width, in dml_core_mode_programming()
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