| /linux/Documentation/arch/x86/ |
| A D | microcode.rst | 18 Early load microcode
32 The microcode files in cpio name space are:
35 kernel/x86/microcode/GenuineIntel.bin
37 kernel/x86/microcode/AuthenticAMD.bin
40 scans the microcode file in the initrd. If microcode matching the
63 DSTDIR=kernel/x86/microcode
103 The loading mechanism looks for microcode blobs in
117 The microcode engine which receives the microcode update is shared
122 Since the microcode can "simulate" MSRs too, while the microcode update
188 Is the microcode suitable for late loading?
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| A D | mds.rst | 77 instruction in combination with a microcode update. The microcode clears
87 executed on a CPU without the microcode update there is no side effect
105 the microcode updated, but the hypervisor does not (yet) expose the
127 scenarios where the host has the updated microcode but the
207 functionality in microcode. Aside of that the IO-Port mechanism is a
209 not affected or do not receive microcode updates anymore.
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| A D | index.rst | 33 microcode
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| /linux/Documentation/arch/powerpc/ |
| A D | qe_firmware.rst | 45 integers that compose the actual QE microcode.
50 1) describes the microcode's purpose
51 2) describes how and where to upload the microcode
62 disables the microcode) must be performed first.
76 in the microcode.
178 the microcode.
211 the microcode to the SOC itself. Normally, the microcode loader should
241 'microcode' (type: struct qe_microcode):
246 identifies this particular microcode.
257 microcode.
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| /linux/arch/x86/kernel/cpu/microcode/ |
| A D | Makefile | 2 microcode-y := core.o
3 obj-$(CONFIG_MICROCODE) += microcode.o
4 microcode-$(CONFIG_CPU_SUP_INTEL) += intel.o
5 microcode-$(CONFIG_CPU_SUP_AMD) += amd.o
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| A D | intel.c | 460 cpu_data(cpu).microcode = uci->cpu_sig.rev; in apply_microcode_late()
462 boot_cpu_data.microcode = uci->cpu_sig.rev; in apply_microcode_late()
469 int cur_rev = boot_cpu_data.microcode; in ucode_validate_minrev()
583 c->microcode < 0x0b000021) { in is_blacklisted()
584 …rr_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode); in is_blacklisted()
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| A D | core.c | 536 int old_rev = boot_cpu_data.microcode; in load_late_stop_cpus()
600 pr_info("revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode); in load_late_stop_cpus()
777 cpu_data(cpu).microcode = uci->cpu_sig.rev; in mc_cpu_online()
779 boot_cpu_data.microcode = uci->cpu_sig.rev; in mc_cpu_online()
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| A D | amd.c | 760 csig->rev = c->microcode; in collect_cpu_info_amd()
812 c->microcode = rev; in apply_microcode_amd()
816 boot_cpu_data.microcode = rev; in apply_microcode_amd()
990 if (c->microcode >= p->patch_id) in load_microcode_amd()
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| /linux/Documentation/power/ |
| A D | suspend-and-cpuhotplug.rst | 176 There are some interesting situations involving CPU hotplug and microcode
179 [Please bear in mind that the kernel requests the microcode images from
187 to apply the same microcode revision to each of the CPUs.
190 and thereby in applying the correct microcode revision to it.
208 (which is sent by the CPU hotplug code), the microcode update driver's
210 microcode image for that CPU.
213 doesn't have the microcode image, it does the CPU type/model discovery
221 have a valid microcode image. This ensures that the CPU type/model
226 d. Handling microcode update during suspend/hibernate:
246 the existing copy of microcode image in the kernel is not freed up.
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| /linux/Documentation/admin-guide/hw-vuln/ |
| A D | gather_data_sampling.rst | 48 This issue is mitigated in microcode. The microcode defines the following new
62 GDS can also be mitigated on systems that don't have updated microcode by
76 use the microcode mitigation when available or disable AVX on affected systems
77 where the microcode hasn't been updated to include the mitigation.
91 Vulnerable: No microcode Processor vulnerable and microcode is missing
94 no microcode Processor is vulnerable and microcode is missing
108 The updated microcode will enable the mitigation by default. The kernel's
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| A D | reg-file-data-sampling.rst | 42 Intel released a microcode update that enables software to clear sensitive
46 unused and obsolete VERW instruction in combination with a microcode update.
47 The microcode clears the affected CPU buffers when the VERW instruction is
58 Newer processors and microcode update on existing affected processors added new
64 microcode that clears the affected buffers on VERW execution.
95 * - 'Vulnerable: No microcode'
96 - The processor is vulnerable but microcode is not updated.
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| A D | tsx_async_abort.rst | 100 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
101 - The processor is vulnerable but microcode is not updated. The
104 If the processor is vulnerable but the availability of the microcode
110 microcode update applied, but the hypervisor is not yet updated to
111 expose the CPUID to the guest. If the host has updated microcode the
135 Affected systems where the host has TAA microcode and TAA is mitigated by
139 In all other cases, if the host either does not have the TAA microcode or
185 and which get the new IA32_TSX_CTRL MSR through a microcode
212 tsx=off tsx_async_abort=full TSX might be disabled if microcode
231 0 0 0 Vulnerable (needs microcode)
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| A D | srso.rst | 36 First of all, it is required that the latest microcode be loaded for
53 * 'Vulnerable: No microcode':
55 The processor is vulnerable, no microcode extending IBPB
58 * 'Vulnerable: Safe RET, no microcode':
61 kernel, but the IBPB-extending microcode has not been applied. User
66 Extended IBPB functionality microcode patch has been applied. It does
83 (spec_rstack_overflow=microcode)
87 Combined microcode/software mitigation. It complements the
88 extended IBPB microcode patch functionality by addressing
139 microcode patch for one's system. This mitigation comes also at
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| A D | special-register-buffer-data-sampling.rst | 64 Intel will release microcode updates that modify the RDRAND, RDSEED, and
86 The microcode updates provide an opt-out mechanism (RNGDS_MITG_DIS) to disable
100 9]==1. This MSR is introduced through the microcode update.
132 Vulnerable: No microcode Processor vulnerable and microcode is missing
147 This new microcode serializes processor access during execution of RDRAND,
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| A D | processor_mmio_stale_data.rst | 14 vulnerabilities includes a combination of microcode update and software
115 Newer processors and microcode update on existing affected processors added new
157 combination with a microcode update. The microcode clears the affected CPU
227 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
228 - The processor is vulnerable but microcode is not updated. The
231 If the processor is vulnerable but the availability of the microcode
237 microcode update applied, but the hypervisor is not yet updated to
238 expose the CPUID to the guest. If the host has updated microcode the
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| A D | mds.rst | 104 * - 'Vulnerable: Clear CPU buffers attempted, no microcode'
105 - The processor is vulnerable but microcode is not updated. The
108 If the processor is vulnerable but the availability of the microcode
114 microcode update applied, but the hypervisor is not yet updated to
115 expose the CPUID to the guest. If the host has updated microcode the
135 The kernel detects the affected CPUs and the presence of the microcode
138 If a CPU is affected and the microcode is available, then the kernel
168 If the L1D flush mitigation is enabled and up to date microcode is
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| /linux/include/trace/events/ |
| A D | mce.h | 45 __field( u32, microcode )
67 __entry->microcode = m->microcode;
86 __entry->microcode)
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| /linux/drivers/net/wireless/intel/iwlegacy/ |
| A D | Kconfig | 22 In order to use this driver, you will need a microcode (uCode)
23 image for it. You can obtain the microcode from:
27 The microcode is typically installed in /lib/firmware. You can
49 In order to use this driver, you will need a microcode (uCode)
50 image for it. You can obtain the microcode from:
54 The microcode is typically installed in /lib/firmware. You can
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| /linux/drivers/crypto/cavium/cpt/ |
| A D | cptpf.h | 22 struct microcode { struct
53 struct microcode mcode[CPT_MAX_CORE_GROUPS]; argument
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| A D | cptpf_main.c | 122 static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode) in cpt_load_microcode()
160 static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode) in do_cpt_init()
257 struct microcode *mcode; in cpt_ucode_load_fw()
417 struct microcode *mcode = &cpt->mcode[grp]; in cpt_unload_microcode()
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| /linux/arch/x86/kernel/cpu/ |
| A D | proc.c | 85 if (c->microcode) in show_cpuinfo()
86 seq_printf(m, "microcode\t: 0x%x\n", c->microcode); in show_cpuinfo()
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| A D | intel.c | 139 u32 microcode; member
179 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
246 c->microcode = intel_get_microcode_revision(); in early_init_intel()
273 c->microcode < 0x20e) { in early_init_intel()
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| A D | match.c | 83 if (!res || res->x86_microcode_rev > boot_cpu_data.microcode) in x86_cpu_has_min_microcode_rev()
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| /linux/arch/x86/include/uapi/asm/ |
| A D | mce.h | 37 __u32 microcode; /* Microcode revision */ member
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| /linux/drivers/soc/fsl/qe/ |
| A D | qe.c | 484 calc_size = struct_size(firmware, microcode, firmware->count); in qe_upload_firmware()
493 be32_to_cpu(firmware->microcode[i].count); in qe_upload_firmware()
535 const struct qe_microcode *ucode = &firmware->microcode[i]; in qe_upload_firmware()
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