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Searched refs:mipi_dsi_dcs_write_seq (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/panel/
A Dpanel-novatek-nt36523.c490 mipi_dsi_dcs_write_seq(dsi, 0xff, 0x20); in j606f_boe_init_sequence()
491 mipi_dsi_dcs_write_seq(dsi, 0xfb, 0x01); in j606f_boe_init_sequence()
492 mipi_dsi_dcs_write_seq(dsi, 0x05, 0xd9); in j606f_boe_init_sequence()
493 mipi_dsi_dcs_write_seq(dsi, 0x07, 0x78); in j606f_boe_init_sequence()
494 mipi_dsi_dcs_write_seq(dsi, 0x08, 0x5a); in j606f_boe_init_sequence()
495 mipi_dsi_dcs_write_seq(dsi, 0x0d, 0x63); in j606f_boe_init_sequence()
496 mipi_dsi_dcs_write_seq(dsi, 0x0e, 0x91); in j606f_boe_init_sequence()
497 mipi_dsi_dcs_write_seq(dsi, 0x0f, 0x73); in j606f_boe_init_sequence()
498 mipi_dsi_dcs_write_seq(dsi, 0x95, 0xeb); in j606f_boe_init_sequence()
499 mipi_dsi_dcs_write_seq(dsi, 0x96, 0xeb); in j606f_boe_init_sequence()
[all …]
A Dpanel-himax-hx83112a.c68 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETPOWER1, in hx83112a_on()
70 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDISP, in hx83112a_on()
73 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDRV, in hx83112a_on()
79 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETDRV, in hx83112a_on()
115 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETTCON, in hx83112a_on()
119 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP0, in hx83112a_on()
128 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP0, in hx83112a_on()
131 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETGIP1, in hx83112a_on()
164 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETTP1, in hx83112a_on()
169 mipi_dsi_dcs_write_seq(dsi, HX83112A_SETTP1, in hx83112a_on()
[all …]
A Dpanel-himax-hx8394.c96 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, in hsd060bhw4_init_sequence()
100 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, in hsd060bhw4_init_sequence()
104 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI, in hsd060bhw4_init_sequence()
108 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP, in hsd060bhw4_init_sequence()
112 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC, in hsd060bhw4_init_sequence()
118 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0, in hsd060bhw4_init_sequence()
125 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1, in hsd060bhw4_init_sequence()
133 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2, in hsd060bhw4_init_sequence()
159 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM, in hsd060bhw4_init_sequence()
213 mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, in powkiddy_x55_init_sequence()
[all …]
A Dpanel-leadtek-ltk050h3146w.c259 mipi_dsi_dcs_write_seq(dsi, 0xd2, 0x88); in ltk050h3148w_init_sequence()
289 mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x0b); in ltk050h3148w_init_sequence()
290 mipi_dsi_dcs_write_seq(dsi, 0xc0, 0x1f, 0x31); in ltk050h3148w_init_sequence()
292 mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x01); in ltk050h3148w_init_sequence()
293 mipi_dsi_dcs_write_seq(dsi, 0xb1, 0x00); in ltk050h3148w_init_sequence()
294 mipi_dsi_dcs_write_seq(dsi, 0xbd, 0x00); in ltk050h3148w_init_sequence()
295 mipi_dsi_dcs_write_seq(dsi, 0xc6, 0xef); in ltk050h3148w_init_sequence()
296 mipi_dsi_dcs_write_seq(dsi, 0xd4, 0x02); in ltk050h3148w_init_sequence()
381 mipi_dsi_dcs_write_seq(dsi, 0xde, 0x02); in ltk050h3146w_init_sequence()
384 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x11); in ltk050h3146w_init_sequence()
[all …]
A Dpanel-visionox-r66451.c48 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00); in visionox_r66451_on()
49 mipi_dsi_dcs_write_seq(dsi, 0xc2, in visionox_r66451_on()
52 mipi_dsi_dcs_write_seq(dsi, 0xd7, in visionox_r66451_on()
56 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x80); in visionox_r66451_on()
57 mipi_dsi_dcs_write_seq(dsi, 0xde, in visionox_r66451_on()
64 mipi_dsi_dcs_write_seq(dsi, 0xc4, in visionox_r66451_on()
67 mipi_dsi_dcs_write_seq(dsi, 0xcf, in visionox_r66451_on()
71 mipi_dsi_dcs_write_seq(dsi, 0xd3, in visionox_r66451_on()
75 mipi_dsi_dcs_write_seq(dsi, 0xd7, in visionox_r66451_on()
79 mipi_dsi_dcs_write_seq(dsi, 0xd8, in visionox_r66451_on()
[all …]
A Dpanel-samsung-s6d7aa0.c70 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0xa5, 0xa5); in s6d7aa0_lock()
71 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0xa5, 0xa5); in s6d7aa0_lock()
73 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0x5a, 0x5a); in s6d7aa0_lock()
75 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0x5a, 0x5a); in s6d7aa0_lock()
76 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0x5a, 0x5a); in s6d7aa0_lock()
249 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x10); in s6d7aa0_lsl080al02_init()
350 mipi_dsi_dcs_write_seq(dsi, 0xb3, 0x51); in s6d7aa0_lsl080al03_init()
357 mipi_dsi_dcs_write_seq(dsi, 0xcd, in s6d7aa0_lsl080al03_init()
360 mipi_dsi_dcs_write_seq(dsi, 0xce, in s6d7aa0_lsl080al03_init()
363 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x03); in s6d7aa0_lsl080al03_init()
[all …]
A Dpanel-xinpeng-xpp055c272.c72 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETMIPI, in xpp055c272_init_sequence()
79 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETRGBIF, in xpp055c272_init_sequence()
82 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETSCR, in xpp055c272_init_sequence()
85 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETVDC, 0x46); in xpp055c272_init_sequence()
86 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPANEL, 0x0b); in xpp055c272_init_sequence()
87 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETCYC, 0x80); in xpp055c272_init_sequence()
89 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETEQ, in xpp055c272_init_sequence()
92 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETPOWER, in xpp055c272_init_sequence()
101 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP1, in xpp055c272_init_sequence()
110 mipi_dsi_dcs_write_seq(dsi, XPP055C272_CMD_SETGIP2, in xpp055c272_init_sequence()
[all …]
A Dpanel-elida-kd35t133.c62 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_POSITIVEGAMMA, in kd35t133_init_sequence()
65 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_NEGATIVEGAMMA, in kd35t133_init_sequence()
68 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_POWERCONTROL1, 0x18, 0x17); in kd35t133_init_sequence()
69 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_POWERCONTROL2, 0x41); in kd35t133_init_sequence()
71 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x48); in kd35t133_init_sequence()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PIXEL_FORMAT, 0x55); in kd35t133_init_sequence()
73 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_INTERFACEMODECTRL, 0x00); in kd35t133_init_sequence()
74 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_FRAMERATECTRL, 0xa0); in kd35t133_init_sequence()
76 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_DISPLAYFUNCTIONCTRL, in kd35t133_init_sequence()
78 mipi_dsi_dcs_write_seq(dsi, KD35T133_CMD_SETIMAGEFUNCTION, 0x00); in kd35t133_init_sequence()
[all …]
A Dpanel-samsung-s6e88a0-ams452ef01.c47 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands in s6e88a0_ams452ef01_on()
48 mipi_dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity in s6e88a0_ams452ef01_on()
58 mipi_dsi_dcs_write_seq(dsi, 0xca, in s6e88a0_ams452ef01_on()
70 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a); in s6e88a0_ams452ef01_on()
71 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage in s6e88a0_ams452ef01_on()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in s6e88a0_ams452ef01_on()
73 mipi_dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update in s6e88a0_ams452ef01_on()
74 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands in s6e88a0_ams452ef01_on()
A Dpanel-raydium-rm69380.c56 mipi_dsi_dcs_write_seq(dsi, 0xfe, 0xd4); in rm69380_on()
57 mipi_dsi_dcs_write_seq(dsi, 0x00, 0x80); in rm69380_on()
58 mipi_dsi_dcs_write_seq(dsi, 0xfe, 0xd0); in rm69380_on()
59 mipi_dsi_dcs_write_seq(dsi, 0x48, 0x00); in rm69380_on()
60 mipi_dsi_dcs_write_seq(dsi, 0xfe, 0x26); in rm69380_on()
61 mipi_dsi_dcs_write_seq(dsi, 0x75, 0x3f); in rm69380_on()
62 mipi_dsi_dcs_write_seq(dsi, 0x1d, 0x1a); in rm69380_on()
63 mipi_dsi_dcs_write_seq(dsi, 0xfe, 0x00); in rm69380_on()
64 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x28); in rm69380_on()
65 mipi_dsi_dcs_write_seq(dsi, 0xc2, 0x08); in rm69380_on()
A Dpanel-boe-bf060y8m-aj0.c61 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0xa5, 0x00); in boe_bf060y8m_aj0_on()
62 mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x00, 0x4c); in boe_bf060y8m_aj0_on()
63 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_3D_CONTROL, 0x10); in boe_bf060y8m_aj0_on()
64 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, DCS_ALLOW_HBM_RANGE); in boe_bf060y8m_aj0_on()
65 mipi_dsi_dcs_write_seq(dsi, 0xf8, in boe_bf060y8m_aj0_on()
75 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0xa5, 0x00); in boe_bf060y8m_aj0_on()
76 mipi_dsi_dcs_write_seq(dsi, 0xc0, in boe_bf060y8m_aj0_on()
79 mipi_dsi_dcs_write_seq(dsi, 0xc1, 0x00, 0x00, 0x00, 0x1f, 0x1f, in boe_bf060y8m_aj0_on()
82 mipi_dsi_dcs_write_seq(dsi, 0xe2, 0x20, 0x04, 0x10, 0x12, 0x92, in boe_bf060y8m_aj0_on()
85 mipi_dsi_dcs_write_seq(dsi, 0xde, 0x01, 0x2c, 0x00, 0x77, 0x3e); in boe_bf060y8m_aj0_on()
A Dpanel-samsung-sofef00.c59 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
67 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
68 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
69 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x07); in sofef00_panel_on()
70 mipi_dsi_dcs_write_seq(dsi, 0xb6, 0x12); in sofef00_panel_on()
71 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); in sofef00_panel_on()
73 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in sofef00_panel_on()
A Dpanel-samsung-s6e3fa7.c60 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in s6e3fa7_panel_on()
61 mipi_dsi_dcs_write_seq(dsi, 0xf4, in s6e3fa7_panel_on()
64 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in s6e3fa7_panel_on()
65 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); in s6e3fa7_panel_on()
A Dpanel-sony-td4353-jdi.c79 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00); in sony_td4353_jdi_on()
87 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_PARTIAL_ROWS, in sony_td4353_jdi_on()
97 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); in sony_td4353_jdi_on()
A Dpanel-ebbg-ft8719.c71 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); in ebbg_ft8719_on()
72 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); in ebbg_ft8719_on()
A Dpanel-sharp-ls060t1sx01.c52 mipi_dsi_dcs_write_seq(dsi, 0xbb, 0x13); in sharp_ls060_on()
53 mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START); in sharp_ls060_on()
/linux/include/drm/
A Ddrm_mipi_dsi.h430 #define mipi_dsi_dcs_write_seq(dsi, cmd, seq...) \ macro
/linux/Documentation/gpu/
A Dtodo.rst502 The macros mipi_dsi_generic_write_seq() and mipi_dsi_dcs_write_seq() are

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