Searched refs:mmUVD_RB_BASE_HI2 (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| A D | uvd_6_0_d.h | 40 #define mmUVD_RB_BASE_HI2 0x3c22 macro
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| A D | uvd_7_0_offset.h | 86 #define mmUVD_RB_BASE_HI2 … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| A D | vcn_1_0_offset.h | 208 #define mmUVD_RB_BASE_HI2 … macro
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| A D | vcn_2_5_offset.h | 563 #define mmUVD_RB_BASE_HI2 … macro
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| A D | vcn_2_0_0_offset.h | 920 #define mmUVD_RB_BASE_HI2 … macro
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| A D | vcn_3_0_0_offset.h | 893 #define mmUVD_RB_BASE_HI2 … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | vcn_v1_0.c | 58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
996 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1296 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
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| A D | vcn_v2_0.c | 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
1140 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1293 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
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| A D | vcn_v2_5.c | 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
1196 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1546 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
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| A D | vcn_v3_0.c | 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
1319 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1695 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
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| A D | uvd_v6_0.c | 878 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
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| A D | uvd_v7_0.c | 1127 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
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