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Searched refs:msg_id (Results 1 – 25 of 138) sorted by relevance

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/linux/include/trace/events/
A Dscmi.h18 __field(u8, msg_id)
26 __entry->msg_id = msg_id;
44 __field(u8, msg_id)
52 __entry->msg_id = msg_id;
70 __field(u8, msg_id)
79 __entry->msg_id = msg_id;
98 __field(u8, msg_id)
106 __entry->msg_id = msg_id;
124 __field(u8, msg_id)
132 __entry->msg_id = msg_id;
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A Dcachefiles.h699 __entry->msg_id = msg->msg_id;
707 __entry->msg_id,
727 __entry->msg_id = msg_id;
733 __entry->msg_id,
750 __entry->msg_id = msg->msg_id;
756 __entry->msg_id,
776 __entry->msg_id = msg->msg_id;
784 __entry->msg_id,
793 TP_ARGS(obj, msg_id),
802 __entry->msg_id = msg_id;
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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu7_clockpowergating.c170 const uint32_t *msg_id) in smu7_update_clock_gatings() argument
182 if (PP_STATE_SUPPORT_CG & *msg_id) { in smu7_update_clock_gatings()
192 if (PP_STATE_SUPPORT_LS & *msg_id) { in smu7_update_clock_gatings()
205 if (PP_STATE_SUPPORT_CG & *msg_id) { in smu7_update_clock_gatings()
229 if (PP_STATE_SUPPORT_LS & *msg_id) { in smu7_update_clock_gatings()
242 if (PP_STATE_SUPPORT_LS & *msg_id) { in smu7_update_clock_gatings()
255 if (PP_STATE_SUPPORT_CG & *msg_id) { in smu7_update_clock_gatings()
276 if (PP_STATE_SUPPORT_CG & *msg_id) { in smu7_update_clock_gatings()
299 if (PP_STATE_SUPPORT_CG & *msg_id) { in smu7_update_clock_gatings()
310 if (PP_STATE_SUPPORT_LS & *msg_id) { in smu7_update_clock_gatings()
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/linux/drivers/media/platform/mediatek/vcodec/encoder/
A Dvenc_ipi_msg.h43 uint32_t msg_id; member
58 uint32_t msg_id; member
82 uint32_t msg_id; member
116 u32 msg_id; member
134 uint32_t msg_id; member
153 uint32_t msg_id; member
171 uint32_t msg_id; member
188 uint32_t msg_id; member
223 uint32_t msg_id; member
239 uint32_t msg_id; member
A Dvenc_vpu_if.c75 mtk_venc_debug(vpu->ctx, "msg_id %x inst %p status %d", msg->msg_id, vpu, msg->status); in vpu_enc_ipi_handler()
76 if (!vpu_enc_check_ap_inst(enc_dev, vpu) || msg->msg_id < VPU_IPIMSG_ENC_INIT_DONE || in vpu_enc_ipi_handler()
77 msg->msg_id > VPU_IPIMSG_ENC_DEINIT_DONE) { in vpu_enc_ipi_handler()
78 mtk_v4l2_venc_err(vpu->ctx, "venc msg id not correctly => 0x%x", msg->msg_id); in vpu_enc_ipi_handler()
89 switch (msg->msg_id) { in vpu_enc_ipi_handler()
101 mtk_venc_err(vpu->ctx, "unknown msg id %x", msg->msg_id); in vpu_enc_ipi_handler()
152 out.msg_id = AP_IPIMSG_ENC_INIT; in vpu_enc_init()
199 out.base.msg_id = AP_IPIMSG_ENC_SET_PARAM; in vpu_enc_set_param()
266 out.base.msg_id = AP_IPIMSG_ENC_ENCODE; in vpu_enc_encode_32bits()
311 out.msg_id = AP_IPIMSG_ENC_ENCODE; in vpu_enc_encode_34bits()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
A Ddcn314_smu.c120 unsigned int msg_id, in dcn314_smu_send_msg_with_param() argument
141 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn314_smu_send_msg_with_param()
150 msg_id == VBIOSSMC_MSG_SetMinDeepSleepDcfclk) in dcn314_smu_send_msg_with_param()
341 unsigned int msg_id, param; in dcn314_smu_set_zstate_support() local
349 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn314_smu_set_zstate_support()
354 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn314_smu_set_zstate_support()
360 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn314_smu_set_zstate_support()
365 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn314_smu_set_zstate_support()
370 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn314_smu_set_zstate_support()
375 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn314_smu_set_zstate_support()
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/linux/include/drm/display/
A Ddrm_hdcp.h152 u8 msg_id; member
165 u8 msg_id; member
170 u8 msg_id; member
175 u8 msg_id; member
180 u8 msg_id; member
185 u8 msg_id; member
190 u8 msg_id; member
195 u8 msg_id; member
201 u8 msg_id; member
209 u8 msg_id; member
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/linux/drivers/media/platform/mediatek/vcodec/decoder/
A Dvdec_ipi_msg.h44 uint32_t msg_id; member
60 uint32_t msg_id; member
72 uint32_t msg_id; member
89 uint32_t msg_id; member
111 uint32_t msg_id; member
128 u32 msg_id; member
145 u32 msg_id; member
A Dvdec_vpu_if.c116 msg->msg_id > VPU_IPIMSG_DEC_GET_PARAM_ACK) { in vpu_dec_ipi_handler()
117 mtk_v4l2_vdec_err(vpu->ctx, "vdec msg id not correctly => 0x%x", msg->msg_id); in vpu_dec_ipi_handler()
126 switch (msg->msg_id) { in vpu_dec_ipi_handler()
143 mtk_vdec_err(vpu->ctx, "invalid msg=%X", msg->msg_id); in vpu_dec_ipi_handler()
182 static int vcodec_send_ap_ipi(struct vdec_vpu_inst *vpu, unsigned int msg_id) in vcodec_send_ap_ipi() argument
187 mtk_vdec_debug(vpu->ctx, "+ id=%X", msg_id); in vcodec_send_ap_ipi()
190 msg.msg_id = msg_id; in vcodec_send_ap_ipi()
198 mtk_vdec_debug(vpu->ctx, "- id=%X ret=%d", msg_id, err); in vcodec_send_ap_ipi()
229 msg.msg_id = AP_IPIMSG_DEC_INIT; in vpu_dec_init()
258 msg.msg_id = AP_IPIMSG_DEC_START; in vpu_dec_start()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
A Ddcn35_smu.c137 unsigned int msg_id, in dcn35_smu_send_msg_with_param() argument
159 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn35_smu_send_msg_with_param()
164 if (msg_id == VBIOSSMC_MSG_TransferTableDram2Smu && in dcn35_smu_send_msg_with_param()
363 unsigned int msg_id, param, retv; in dcn35_smu_set_zstate_support() local
371 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn35_smu_set_zstate_support()
377 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn35_smu_set_zstate_support()
384 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn35_smu_set_zstate_support()
390 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn35_smu_set_zstate_support()
396 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn35_smu_set_zstate_support()
402 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn35_smu_set_zstate_support()
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/linux/drivers/media/platform/mediatek/mdp/
A Dmtk_mdp_vpu.c33 unsigned int msg_id = msg->msg_id; in mtk_mdp_vpu_ipi_handler() local
40 switch (msg_id) { in mtk_mdp_vpu_ipi_handler()
51 msg_id); in mtk_mdp_vpu_ipi_handler()
57 msg_id, vpu->failure); in mtk_mdp_vpu_ipi_handler()
96 static int mtk_mdp_vpu_send_ap_ipi(struct mtk_mdp_vpu *vpu, uint32_t msg_id) in mtk_mdp_vpu_send_ap_ipi() argument
101 msg.msg_id = msg_id; in mtk_mdp_vpu_send_ap_ipi()
120 msg.msg_id = AP_MDP_INIT; in mtk_mdp_vpu_init()
A Dmtk_mdp_ipi.h32 uint32_t msg_id; member
46 uint32_t msg_id; member
62 uint32_t msg_id; member
/linux/drivers/gpu/drm/amd/display/dc/hdcp/
A Dhdcp_msg.c138 if (message_info->msg_id == HDCP_MESSAGE_ID_INVALID) { in hdmi_14_process_transaction()
139 DC_LOG_ERROR("%s: Invalid message_info msg_id - %d\n", __func__, message_info->msg_id); in hdmi_14_process_transaction()
143 offset = hdcp_i2c_offsets[message_info->msg_id]; in hdmi_14_process_transaction()
158 if (hdcp_cmd_is_read[message_info->msg_id]) { in hdmi_14_process_transaction()
319 if (message_info->msg_id == HDCP_MESSAGE_ID_INVALID) { in dp_11_process_transaction()
320 DC_LOG_ERROR("%s: Invalid message_info msg_id - %d\n", __func__, message_info->msg_id); in dp_11_process_transaction()
328 hdcp_dpcd_addrs[message_info->msg_id], in dp_11_process_transaction()
329 hdcp_cmd_is_read[message_info->msg_id]); in dp_11_process_transaction()
395 if (message_info->msg_id < HDCP_MESSAGE_ID_READ_BKSV || in dc_process_hdcp_msg()
396 message_info->msg_id >= HDCP_MESSAGE_ID_MAX) in dc_process_hdcp_msg()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_smu.c104 unsigned int msg_id, in dcn31_smu_send_msg_with_param() argument
125 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); in dcn31_smu_send_msg_with_param()
130 if (msg_id == VBIOSSMC_MSG_TransferTableDram2Smu && in dcn31_smu_send_msg_with_param()
141 dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); in dcn31_smu_send_msg_with_param()
322 unsigned int msg_id, param; in dcn31_smu_set_zstate_support() local
338 msg_id = VBIOSSMC_MSG_DisallowZstatesEntry; in dcn31_smu_set_zstate_support()
340 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; in dcn31_smu_set_zstate_support()
344 msg_id, in dcn31_smu_set_zstate_support()
/linux/drivers/net/ethernet/huawei/hinic/
A Dhinic_hw_mgmt.c130 u16 cmd, u16 msg_id) in prepare_header() argument
145 HINIC_MSG_HEADER_SET(msg_id, MSG_ID); in prepare_header()
209 u16 msg_id; in send_msg_to_mgmt() local
211 msg_id = SYNC_MSG_ID(pf_to_mgmt); in send_msg_to_mgmt()
219 direction, cmd, msg_id); in send_msg_to_mgmt()
257 u16 msg_id; in msg_to_mgmt_sync() local
267 msg_id = SYNC_MSG_ID(pf_to_mgmt); in msg_to_mgmt_sync()
269 msg_id = resp_msg_id; in msg_to_mgmt_sync()
291 if (recv_msg->msg_id != msg_id) { in msg_to_mgmt_sync()
428 mgmt_work->msg_id); in recv_mgmt_msg_work_handler()
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/linux/sound/soc/intel/atom/sst/
A Dsst_ipc.c29 u32 msg_id, u32 drv_id) in sst_create_block() argument
39 msg->msg_id = msg_id; in sst_create_block()
72 dev_dbg(ctx->dev, "Block ipc %d, drv_id %d\n", block->msg_id, in sst_wake_up_block()
74 if (block->msg_id == ipc && block->drv_id == drv_id) { in sst_wake_up_block()
251 u32 msg_id; in process_fw_async_msg() local
259 msg_id = ((struct ipc_dsp_hdr *)msg->mailbox_data)->cmd_id; in process_fw_async_msg()
263 switch (msg_id) { in process_fw_async_msg()
314 "Unrecognized async msg from FW msg_id %#x\n", msg_id); in process_fw_async_msg()
349 msg_high.part.msg_id, NULL, 0); in sst_process_reply_mrfld()
367 msg_high.part.msg_id, data, msg_low)) in sst_process_reply_mrfld()
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/linux/drivers/gpu/drm/i915/display/
A Dintel_dp_hdcp.c290 u8 msg_id; member
295 u8 msg_id; member
363 u8 msg_id, bool *msg_ready) in hdcp2_detect_msg_availability() argument
373 switch (msg_id) { in hdcp2_detect_msg_availability()
388 "Unidentified msg_id: %d\n", msg_id); in hdcp2_detect_msg_availability()
403 u8 msg_id = hdcp2_msg_data->msg_id; in intel_dp_hdcp2_wait_for_msg() local
434 hdcp2_msg_data->msg_id, ret, timeout); in intel_dp_hdcp2_wait_for_msg()
444 if (hdcp2_dp_msg_data[i].msg_id == msg_id) in get_hdcp2_dp_msg_data()
514 u8 msg_id, void *buf, size_t size) in intel_dp_hdcp2_read_msg() argument
571 msg_id, ret); in intel_dp_hdcp2_read_msg()
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/linux/drivers/net/can/esd/
A Desdacc.h130 u8 msg_id; member
148 u8 msg_id; member
159 u8 msg_id; member
170 u8 msg_id; member
183 u8 msg_id; member
194 u8 msg_id; member
204 u8 msg_id; member
212 u8 msg_id; member
218 u8 msg_id; member
/linux/include/linux/soc/qcom/
A Dqmi.h28 u16 msg_id; member
190 unsigned int msg_id; member
251 struct qmi_txn *txn, int msg_id, size_t len,
254 struct qmi_txn *txn, int msg_id, size_t len,
257 int msg_id, size_t len, const struct qmi_elem_info *ei,
260 void *qmi_encode_message(int type, unsigned int msg_id, size_t *len,
/linux/drivers/platform/x86/amd/
A Dhsmp.c217 msg->msg_id, mbox_status); in __hsmp_send_message()
234 ret, index, msg->msg_id); in __hsmp_send_message()
246 if (msg->msg_id < HSMP_TEST || msg->msg_id >= HSMP_MSG_ID_MAX) in validate_message()
303 msg.msg_id = HSMP_TEST; in hsmp_test()
337 if (msg.msg_id < HSMP_TEST || msg.msg_id >= HSMP_MSG_ID_MAX) in hsmp_ioctl()
346 if (hsmp_msg_desc_table[msg.msg_id].type != HSMP_SET) in hsmp_ioctl()
354 if (hsmp_msg_desc_table[msg.msg_id].type != HSMP_GET) in hsmp_ioctl()
371 if (hsmp_msg_desc_table[msg.msg_id].response_sz > 0) { in hsmp_ioctl()
578 msg.msg_id = HSMP_GET_METRIC_TABLE; in hsmp_metric_tbl_read()
598 msg.msg_id = HSMP_GET_METRIC_TABLE_DRAM_ADDR; in hsmp_get_tbl_dram_base()
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/linux/drivers/gpu/drm/amd/display/modules/hdcp/
A Dhdcp_ddc.c153 enum mod_hdcp_ddc_message_id msg_id, in read() argument
162 msg_id >= MOD_HDCP_MESSAGE_ID_MAX) in read()
167 if (msg_id >= num_dpcd_addrs) in read()
185 if (msg_id >= num_i2c_offsets) in read()
191 hdcp_i2c_offsets[msg_id], in read()
200 enum mod_hdcp_ddc_message_id msg_id, in read_repeatedly() argument
224 enum mod_hdcp_ddc_message_id msg_id, in write() argument
233 msg_id >= MOD_HDCP_MESSAGE_ID_MAX) in write()
238 if (msg_id >= num_dpcd_addrs) in write()
257 if (msg_id >= num_i2c_offsets) in write()
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/linux/drivers/infiniband/ulp/rtrs/
A Drtrs-srv-trace.h43 __field(u32, msg_id)
61 __entry->msg_id = id->msg_id;
76 __entry->msg_id,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr_smu_msg.c71 static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32… in dcn32_smu_send_msg_with_param() argument
83 REG_WRITE(DAL_MSG_REG, msg_id); in dcn32_smu_send_msg_with_param()
85 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn32_smu_send_msg_with_param()
128 static bool dcn32_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, … in dcn32_smu_send_msg_with_param_delay() argument
143 REG_WRITE(DAL_MSG_REG, msg_id); in dcn32_smu_send_msg_with_param_delay()
145 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn32_smu_send_msg_with_param_delay()
/linux/drivers/soc/qcom/
A Dsmd-rpm.c55 __le32 msg_id; member
75 __le32 msg_id; member
100 static unsigned msg_id = 1; in qcom_rpm_smd_write() local
123 pkt->req.msg_id = cpu_to_le32(msg_id++); in qcom_rpm_smd_write()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr_smu_msg.c47 static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint3… in dcn401_smu_send_msg_with_param() argument
59 REG_WRITE(DAL_MSG_REG, msg_id); in dcn401_smu_send_msg_with_param()
102 static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id,… in dcn401_smu_send_msg_with_param_delay() argument
117 REG_WRITE(DAL_MSG_REG, msg_id); in dcn401_smu_send_msg_with_param_delay()
119 TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); in dcn401_smu_send_msg_with_param_delay()

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