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Searched refs:mtk_phy_update_bits (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/phy/mediatek/
A Dphy-mtk-xfi-tphy.c120 mtk_phy_update_bits(xfi_tphy->base + 0x2030, 0x500, is_1g ? 0x0 : 0x500); in mtk_xfi_tphy_setup()
137 mtk_phy_update_bits(xfi_tphy->base + 0x5084, 0x30300, is_1g ? 0x30300 : in mtk_xfi_tphy_setup()
140 mtk_phy_update_bits(xfi_tphy->base + 0x5088, 0x60200, is_1g ? 0x20200 : in mtk_xfi_tphy_setup()
162 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_F4, in mtk_xfi_tphy_setup()
179 mtk_phy_update_bits(xfi_tphy->base + 0x30b0, 0x30, 0x20); in mtk_xfi_tphy_setup()
202 mtk_phy_update_bits(xfi_tphy->base + 0x3050, 0xa8000000, in mtk_xfi_tphy_setup()
204 mtk_phy_update_bits(xfi_tphy->base + 0x3054, 0xaa, in mtk_xfi_tphy_setup()
219 mtk_phy_update_bits(xfi_tphy->base + REG_ANA_GLB_D0, in mtk_xfi_tphy_setup()
233 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70, in mtk_xfi_tphy_setup()
249 mtk_phy_update_bits(xfi_tphy->base + REG_DIG_GLB_70, in mtk_xfi_tphy_setup()
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A Dphy-mtk-hdmi-mt8173.c162 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
167 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
172 mtk_phy_update_bits(base + HDMI_CON0, in mtk_hdmi_pll_set_rate()
189 mtk_phy_update_bits(base + HDMI_CON4, in mtk_hdmi_pll_set_rate()
197 mtk_phy_update_bits(base + HDMI_CON6, in mtk_hdmi_pll_set_rate()
204 mtk_phy_update_bits(base + HDMI_CON5, in mtk_hdmi_pll_set_rate()
A Dphy-mtk-mipi-dsi-mt8173.c155 mtk_phy_update_bits(base + MIPITX_DSI_BG_CON, in mtk_mipi_tx_pll_prepare()
168 mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_pll_prepare()
176 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, in mtk_mipi_tx_pll_prepare()
182 mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0, in mtk_mipi_tx_pll_prepare()
225 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, in mtk_mipi_tx_pll_unprepare()
A Dphy-mtk-io.h30 static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val) in mtk_phy_update_bits() function
43 mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val)); \
A Dphy-mtk-tphy.c804 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1, in u3_phy_instance_init()
976 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, in pcie_phy_instance_init()
992 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5, in pcie_phy_instance_init()
997 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4, in pcie_phy_instance_init()
1049 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6, in sata_phy_instance_init()
1058 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4, in sata_phy_instance_init()
1063 mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4, in sata_phy_instance_init()
1070 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, in sata_phy_instance_init()
1075 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, in sata_phy_instance_init()
A Dphy-mtk-mipi-dsi-mt8183.c126 mtk_phy_update_bits(mipi_tx->regs + in mtk_mipi_tx_config_calibration_data()
A Dphy-mtk-xsphy.c186 mtk_phy_update_bits(pbase + XSP_U2PHYDTM1, in u2_phy_instance_power_on()
201 mtk_phy_update_bits(pbase + XSP_U2PHYDTM1, in u2_phy_instance_power_off()

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