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/linux/drivers/clk/
A Dclk-multiplier.c18 return ioread32be(mult->reg); in clk_mult_readl()
20 return readl(mult->reg); in clk_mult_readl()
26 iowrite32be(val, mult->reg); in clk_mult_writel()
28 writel(val, mult->reg); in clk_mult_writel()
47 val = clk_mult_readl(mult) >> mult->shift; in clk_multiplier_recalc_rate()
120 mult->width, mult->flags); in clk_multiplier_round_rate()
133 if (mult->lock) in clk_multiplier_set_rate()
136 __acquire(mult->lock); in clk_multiplier_set_rate()
139 val &= ~GENMASK(mult->width + mult->shift - 1, mult->shift); in clk_multiplier_set_rate()
143 if (mult->lock) in clk_multiplier_set_rate()
[all …]
A Dclk-fixed-factor.c45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
116 fix->mult = mult; in __clk_hw_register_fixed_factor()
165 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor_index() argument
170 flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor_index()
211 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor() argument
239 &pdata, flags, mult, div, acc, in clk_hw_register_fixed_factor_with_accuracy_fwname()
246 unsigned int mult, unsigned int div) in clk_register_fixed_factor() argument
284 unsigned int mult, unsigned int div) in devm_clk_hw_register_fixed_factor() argument
289 &pdata, flags, mult, div, 0, 0, true); in devm_clk_hw_register_fixed_factor()
312 &pdata, flags, mult, div, acc, in devm_clk_hw_register_fixed_factor_with_accuracy_fwname()
[all …]
/linux/drivers/clk/sunxi-ng/
A Dccu_mult.c23 if (_mult < mult->min) in ccu_mult_find_best()
24 _mult = mult->min; in ccu_mult_find_best()
26 if (_mult > mult->max) in ccu_mult_find_best()
27 _mult = mult->max; in ccu_mult_find_best()
29 mult->mult = _mult; in ccu_mult_find_best()
43 if (cm->mult.max) in ccu_mult_round_rate()
46 _cm.max = (1 << cm->mult.width) + cm->mult.offset - 1; in ccu_mult_round_rate()
125 if (cm->mult.max) in ccu_mult_set_rate()
128 _cm.max = (1 << cm->mult.width) + cm->mult.offset - 1; in ccu_mult_set_rate()
135 reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift); in ccu_mult_set_rate()
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/linux/arch/mips/boot/dts/mobileye/
A Deyeq5-clocks.dtsi22 clock-mult = <1>;
29 clock-mult = <1>;
36 clock-mult = <1>;
43 clock-mult = <1>;
50 clock-mult = <1>;
57 clock-mult = <1>;
64 clock-mult = <1>;
71 clock-mult = <1>;
78 clock-mult = <1>;
85 clock-mult = <1>;
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/linux/drivers/clk/renesas/
A Drcar-gen3-cpg.c56 unsigned int mult; in cpg_pll_clk_recalc_rate() local
79 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate()
89 unsigned int mult, i; in cpg_pll_clk_set_rate() local
93 mult = clamp(mult, 1U, 128U); in cpg_pll_clk_set_rate()
119 unsigned int mult, in cpg_pll_clk_register() argument
179 unsigned int mult; in cpg_z_clk_recalc_rate() local
214 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
224 unsigned int mult; in cpg_z_clk_set_rate() local
229 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
353 unsigned int mult = 1; in rcar_gen3_cpg_clk_register() local
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A Drcar-gen2-cpg.c57 unsigned int mult; in cpg_z_clk_recalc_rate() local
61 mult = 32 - val; in cpg_z_clk_recalc_rate()
78 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
88 unsigned int mult; in cpg_z_clk_set_rate() local
93 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
176 fixed->mult = 1; in cpg_rcan_clk_register()
283 unsigned int mult = 1; in rcar_gen2_cpg_clk_register() local
306 mult = cpg_pll_config->pll0_mult; in rcar_gen2_cpg_clk_register()
308 if (!mult) { in rcar_gen2_cpg_clk_register()
321 mult = cpg_pll_config->pll3_mult; in rcar_gen2_cpg_clk_register()
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A Dclk-sh73a0.c78 unsigned int mult = 1; in sh73a0_cpg_register_clock() local
109 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1; in sh73a0_cpg_register_clock()
113 mult *= 2; in sh73a0_cpg_register_clock()
121 mult = readl(dsi_reg); in sh73a0_cpg_register_clock()
122 if (!(mult & 0x8000)) in sh73a0_cpg_register_clock()
123 mult = 1; in sh73a0_cpg_register_clock()
125 mult = (mult & 0x3f) + 1; in sh73a0_cpg_register_clock()
151 mult, div); in sh73a0_cpg_register_clock()
A Drcar-gen4-cpg.c282 unsigned int mult; in cpg_z_clk_recalc_rate() local
286 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
296 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
317 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
327 unsigned int mult; in cpg_z_clk_set_rate() local
332 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
425 unsigned int mult = 1; in rcar_gen4_cpg_clk_register() local
439 mult = cpg_pll_config->pll1_mult; in rcar_gen4_cpg_clk_register()
444 mult = cpg_pll_config->pll5_mult; in rcar_gen4_cpg_clk_register()
501 mult = 1; in rcar_gen4_cpg_clk_register()
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A Dclk-rz.c51 unsigned mult; in rz_cpg_register_clock() local
58 mult = cpg_mode ? (32 / 4) : 30; in rz_cpg_register_clock()
60 return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1); in rz_cpg_register_clock()
78 mult = frqcr_tab[val]; in rz_cpg_register_clock()
79 return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3); in rz_cpg_register_clock()
/linux/drivers/clk/imx/
A Dclk-pllv4.c82 u32 mult, mfn, mfd; in clk_pllv4_recalc_rate() local
86 mult &= BM_PLL_MULT; in clk_pllv4_recalc_rate()
87 mult >>= BP_PLL_MULT; in clk_pllv4_recalc_rate()
107 u32 mult; in clk_pllv4_round_rate() local
112 mult = temp64; in clk_pllv4_round_rate()
113 if (mult >= pllv4_mult_range[1] && in clk_pllv4_round_rate()
115 round_rate = parent_rate * mult; in clk_pllv4_round_rate()
165 mult <= pllv4_mult_range[0]) in clk_pllv4_is_valid_mult()
169 if (pllv4_mult_table[i] == mult) in clk_pllv4_is_valid_mult()
184 mult = rate / parent_rate; in clk_pllv4_set_rate()
[all …]
/linux/drivers/clk/mvebu/
A Dorion.c65 *mult = 1; in mv88f5181_get_clk_ratio()
68 *mult = 1; in mv88f5181_get_clk_ratio()
71 *mult = 0; in mv88f5181_get_clk_ratio()
133 *mult = 1; in mv88f5182_get_clk_ratio()
136 *mult = 1; in mv88f5182_get_clk_ratio()
139 *mult = 0; in mv88f5182_get_clk_ratio()
190 *mult = 1; in mv88f5281_get_clk_ratio()
193 *mult = 1; in mv88f5281_get_clk_ratio()
196 *mult = 0; in mv88f5281_get_clk_ratio()
256 *mult = 1; in mv88f6183_get_clk_ratio()
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A Dmv98dx3236.c118 void __iomem *sar, int id, int *mult, int *div) in mv98dx3236_get_clk_ratio() argument
126 *mult = mv98dx4251_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
129 *mult = mv98dx3236_cpu_ddr_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
135 *mult = mv98dx4251_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
138 *mult = mv98dx3236_cpu_mpll_ratios[opt][0]; in mv98dx3236_get_clk_ratio()
/linux/drivers/clk/sunxi/
A Dclk-sun4i-pll3.c24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
48 mult = kzalloc(sizeof(*mult), GFP_KERNEL); in sun4i_a10_pll3_setup()
49 if (!mult) in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
53 mult->shift = SUN4I_A10_PLL3_DIV_SHIFT; in sun4i_a10_pll3_setup()
54 mult->width = SUN4I_A10_PLL3_DIV_WIDTH; in sun4i_a10_pll3_setup()
55 mult->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
60 &mult->hw, &clk_multiplier_ops, in sun4i_a10_pll3_setup()
80 kfree(mult); in sun4i_a10_pll3_setup()
A Dclk-a10-pll2.c44 struct clk_multiplier *mult; in sun4i_pll2_setup() local
83 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); in sun4i_pll2_setup()
84 if (!mult) in sun4i_pll2_setup()
87 mult->reg = reg; in sun4i_pll2_setup()
88 mult->shift = SUN4I_PLL2_N_SHIFT; in sun4i_pll2_setup()
89 mult->width = 7; in sun4i_pll2_setup()
90 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | in sun4i_pll2_setup()
92 mult->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup()
98 &mult->hw, &clk_multiplier_ops, in sun4i_pll2_setup()
168 kfree(mult); in sun4i_pll2_setup()
/linux/drivers/iio/common/inv_sensors/
A Dinv_sensors_timestamp.c52 ts->mult = chip->init_period / chip->clock_period; in inv_sensors_timestamp_init()
63 uint32_t mult; in inv_sensors_timestamp_update_odr() local
69 mult = period / ts->chip.clock_period; in inv_sensors_timestamp_update_odr()
70 if (mult != ts->mult) in inv_sensors_timestamp_update_odr()
71 ts->new_mult = mult; in inv_sensors_timestamp_update_odr()
82 period_min = ts->min_period * ts->mult; in inv_validate_period()
83 period_max = ts->max_period * ts->mult; in inv_validate_period()
99 new_chip_period = period / ts->mult; in inv_update_chip_period()
101 ts->period = ts->mult * ts->chip_period.val; in inv_update_chip_period()
178 ts->mult = ts->new_mult; in inv_sensors_timestamp_apply_odr()
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/linux/include/linux/
A Drandom.h78 u32 mult = ceil * get_random_u8(); in get_random_u32_below() local
79 if (likely(is_power_of_2(ceil) || (u8)mult >= (1U << 8) % ceil)) in get_random_u32_below()
80 return mult >> 8; in get_random_u32_below()
82 u32 mult = ceil * get_random_u16(); in get_random_u32_below() local
83 if (likely(is_power_of_2(ceil) || (u16)mult >= (1U << 16) % ceil)) in get_random_u32_below()
84 return mult >> 16; in get_random_u32_below()
86 u64 mult = (u64)ceil * get_random_u32(); in get_random_u32_below() local
87 if (likely(is_power_of_2(ceil) || (u32)mult >= -ceil % ceil)) in get_random_u32_below()
88 return mult >> 32; in get_random_u32_below()
/linux/arch/arm/mach-omap2/
A Dclkt2xxx_dpllcore.c113 u32 cur_rate, low, mult, div, valid_rate, done_rate; in omap2_reprogram_dpllcore() local
119 mult = omap2xxx_cm_get_core_clk_src(); in omap2_reprogram_dpllcore()
121 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore()
123 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore()
130 if (mult == 1) in omap2_reprogram_dpllcore()
148 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore()
152 mult = (rate / 1000000); in omap2_reprogram_dpllcore()
156 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); in omap2_reprogram_dpllcore()
/linux/sound/core/
A Dpcm_timer.c21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local
24 mult = 1000000000; in snd_pcm_timer_resolution_change()
28 l = gcd(mult, rate); in snd_pcm_timer_resolution_change()
29 mult /= l; in snd_pcm_timer_resolution_change()
38 while ((mult * fsize) / fsize != mult) { in snd_pcm_timer_resolution_change()
39 mult /= 2; in snd_pcm_timer_resolution_change()
49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
/linux/arch/arm/boot/dts/ti/omap/
A Domap36xx-omap3430es2plus-clocks.dtsi51 clock-mult = <1>;
83 clock-mult = <1>;
107 clock-mult = <1>;
115 clock-mult = <1>;
123 clock-mult = <1>;
131 clock-mult = <1>;
139 clock-mult = <1>;
147 clock-mult = <1>;
155 clock-mult = <1>;
163 clock-mult = <1>;
[all …]
A Dam33xx-clocks.dtsi22 clock-mult = <1>;
31 clock-mult = <1>;
40 clock-mult = <1>;
49 clock-mult = <1>;
58 clock-mult = <1>;
67 clock-mult = <1>;
76 clock-mult = <1>;
85 clock-mult = <1>;
94 clock-mult = <1>;
103 clock-mult = <1>;
[all …]
/linux/sound/soc/codecs/
A Des8311.c328 unsigned int mult; member
383 unsigned int mult = coeff->mult; in es8311_cmp_adj_mclk_coeff() local
395 if (mult == 2 || mult == 4 || mult == 8) { in es8311_cmp_adj_mclk_coeff()
396 mult *= coeff->mult; in es8311_cmp_adj_mclk_coeff()
397 if (mult <= 8) in es8311_cmp_adj_mclk_coeff()
406 out_coeff->mult = mult; in es8311_cmp_adj_mclk_coeff()
562 unsigned int mult; in es8311_hw_params() local
566 mult = 0; in es8311_hw_params()
569 mult = 1; in es8311_hw_params()
572 mult = 2; in es8311_hw_params()
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/linux/drivers/thermal/broadcom/
A Dbrcmstb_thermal.c107 unsigned int mult; member
124 int mult = priv->temp_params->mult; in avs_tmon_code_to_temp() local
126 return (offset - (int)((code & AVS_TMON_TEMP_MASK) * mult)); in avs_tmon_code_to_temp()
139 int mult = priv->temp_params->mult; in avs_tmon_temp_to_code() local
148 return (u32)(DIV_ROUND_UP(offset - temp, mult)); in avs_tmon_temp_to_code()
150 return (u32)((offset - temp) / mult); in avs_tmon_temp_to_code()
295 .mult = 557,
306 .mult = 487,
/linux/drivers/net/ethernet/pensando/ionic/
A Dionic_phc.c311 ctx->cmd.lif_setphc.mult = cpu_to_le32(phc->cc.mult); in ionic_setphc_cmd()
342 phc->cc.mult = adj; in ionic_phc_adjfine()
524 u64 delay, diff, mult; in ionic_lif_alloc_phc() local
547 if (!phc->cc.mult) { in ionic_lif_alloc_phc()
550 phc->cc.mult); in ionic_lif_alloc_phc()
557 phc->cc.mask, phc->cc.mult, phc->cc.shift); in ionic_lif_alloc_phc()
567 diff = U64_MAX / phc->cc.mult / 2; in ionic_lif_alloc_phc()
571 diff = DIV_ROUND_UP(diff, phc->cc.mult); in ionic_lif_alloc_phc()
603 shift = mult / phc->cc.mult; in ionic_lif_alloc_phc()
608 phc->cc.mult <<= shift; in ionic_lif_alloc_phc()
[all …]
/linux/drivers/clk/davinci/
A Dpll.c119 u32 mult; in davinci_pll_recalc_rate() local
122 rate *= mult + 1; in davinci_pll_recalc_rate()
135 u32 mult; in davinci_pll_determine_rate() local
142 mult = rate / parent_rate; in davinci_pll_determine_rate()
150 if (mult < pll->pllm_min || mult > pll->pllm_max) in davinci_pll_determine_rate()
161 for (mult = pll->pllm_min; mult <= pll->pllm_max; mult++) { in davinci_pll_determine_rate()
163 r = parent_rate * mult; in davinci_pll_determine_rate()
184 u32 mult; in davinci_pll_set_rate() local
186 mult = rate / parent_rate; in davinci_pll_set_rate()
211 u32 mult; in dm365_pll_recalc_rate() local
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/linux/kernel/time/
A Dsched_clock.c62 .read_data[0] = { .mult = NSEC_PER_SEC / HZ,
67 static __always_inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift) in cyc_to_ns() argument
69 return (cyc * mult) >> shift; in cyc_to_ns()
95 res = rd->epoch_ns + cyc_to_ns(cyc, rd->mult, rd->shift); in sched_clock_noinstr()
147 ns = rd.epoch_ns + cyc_to_ns((cyc - rd.epoch_cyc) & rd.sched_clock_mask, rd.mult, rd.shift); in update_sched_clock()
193 ns = rd.epoch_ns + cyc_to_ns((cyc - rd.epoch_cyc) & rd.sched_clock_mask, rd.mult, rd.shift); in sched_clock_register()
198 rd.mult = new_mult; in sched_clock_register()

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