Searched refs:native_420 (Results 1 – 10 of 10) sorted by relevance
52 pps->native_420 ? CM_420 : CM_444)); in calc_rc_params()56 is_navite_422_or_420 = pps->native_422 || pps->native_420; in calc_rc_params()
38 to->native_420 = from->native_420; in copy_pps_fields()
63 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()65 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()107 if (vdsc_cfg->native_420) { in calculate_rc_params()138 if (vdsc_cfg->native_420) { in calculate_rc_params()291 vdsc_cfg->native_420 = true; in intel_dsc_compute_params()304 if (vdsc_cfg->native_420) in intel_dsc_compute_params()447 if (vdsc_cfg->native_420) in intel_dsc_pps_configure()854 vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE; in intel_dsc_get_pps_config()862 if (vdsc_cfg->native_420) in intel_dsc_get_pps_config()
5446 PIPE_CONF_CHECK_BOOL(dsc.config.native_420); in intel_pipe_config_compare()
133 if (dsc->native_420) in dpu_hw_dsc_config_1_2()141 if (dsc->native_422 || dsc->native_420) in dpu_hw_dsc_config_1_2()225 else if (dsc->native_420) in dpu_hw_dsc_config_1_2()
253 bool native_420; member
256 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; in drm_dsc_pps_payload_pack()1322 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()1489 str_yes_no(cfg->simple_422), str_yes_no(cfg->native_422), str_yes_no(cfg->native_420)); in drm_dsc_dump_config_main_params()
320 DC_LOG_DSC("\tnative_420 %d", pps->native_420); in dsc_log_pps()435 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); in dsc_prepare_config()
266 bool native_420; member
6132 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; in drm_parse_dsc_info()
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