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Searched refs:num_dwb (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
A Ddcn30_hwseq.h52 unsigned int num_dwb,
A Ddcn30_hwseq.c451 unsigned int num_dwb, in dcn30_mmhubbub_warmup() argument
459 for (i = 0; i < num_dwb; i++) { in dcn30_mmhubbub_warmup()
488 for (i = 0; i < num_dwb; i++) { in dcn30_mmhubbub_warmup()
575 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
605 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
A Ddcn302_resource.c128 .num_dwb = 1,
711 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
746 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1062 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
A Ddcn303_resource.c126 .num_dwb = 1,
673 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
708 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
1007 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dresource.h52 int num_dwb; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
A Ddcn301_resource.c647 .num_dwb = 1,
1111 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1179 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1204 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc_stream.h448 int num_dwb,
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
A Ddcn316_resource.c817 .num_dwb = 1,
1437 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1510 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1535 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
A Ddcn314_resource.c835 .num_dwb = 1,
1497 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1573 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1598 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_stream.c616 int num_dwb, in dc_stream_warmup_writeback() argument
622 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info); in dc_stream_warmup_writeback()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
A Ddcn31_resource.c823 .num_dwb = 1,
1441 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1517 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
A Ddcn315_resource.c822 .num_dwb = 1,
1441 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1517 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
A Ddcn35_resource.c677 .num_dwb = 1,
1510 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1602 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1641 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
A Ddcn321_resource.c651 .num_dwb = 1,
1427 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1488 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1517 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
A Ddcn351_resource.c657 .num_dwb = 1,
1490 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1582 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1621 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c662 .num_dwb = 1,
700 .num_dwb = 1,
1149 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
2267 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2290 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
A Ddcn401_resource.c650 .num_dwb = 1,
1426 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn401_resource_destruct()
1487 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_dwbc_create()
1518 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/hwss/
A Dhw_sequencer.h335 unsigned int num_dwb,
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.c676 .num_dwb = 1,
1140 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1219 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1244 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource.c654 .num_dwb = 1,
1445 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1506 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1535 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
A Ddcn201_hwseq.c330 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
A Ddcn21_resource.c578 .num_dwb = 1,
719 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
A Ddcn201_resource.c569 .num_dwb = 0,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c3163 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn20_fpga_init_hw()

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