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Searched refs:num_levels (Results 1 – 25 of 67) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c122 clks->num_levels = 6; in get_default_clock_levels()
127 clks->num_levels = 6; in get_default_clock_levels()
132 clks->num_levels = 2; in get_default_clock_levels()
137 clks->num_levels = 0; in get_default_clock_levels()
226 dc_clks->num_levels = pp_clks->count; in pp_to_dc_clock_levels()
247 pp_clks->num_levels, in pp_to_dc_clock_levels_with_latency()
252 clk_level_info->num_levels = pp_clks->num_levels; in pp_to_dc_clock_levels_with_latency()
274 pp_clks->num_levels, in pp_to_dc_clock_levels_with_voltage()
279 clk_level_info->num_levels = pp_clks->num_levels; in pp_to_dc_clock_levels_with_voltage()
340 dc_clks->num_levels, i); in dm_pp_get_clock_levels_by_type()
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/linux/drivers/video/backlight/
A Dled_bl.c127 int num_levels; in led_bl_parse_levels() local
134 num_levels = of_property_count_u32_elems(node, "brightness-levels"); in led_bl_parse_levels()
135 if (num_levels > 1) { in led_bl_parse_levels()
140 levels = devm_kzalloc(dev, sizeof(u32) * num_levels, in led_bl_parse_levels()
147 num_levels); in led_bl_parse_levels()
156 for (i = 0 ; i < num_levels; i++) { in led_bl_parse_levels()
161 priv->max_brightness = num_levels - 1; in led_bl_parse_levels()
163 } else if (num_levels >= 0) in led_bl_parse_levels()
A Dmp3309c.c205 int num_levels; in mp3309c_parse_fwnode() local
238 num_levels = ANALOG_I2C_NUM_LEVELS; in mp3309c_parse_fwnode()
251 num_levels = device_property_count_u32(dev, "brightness-levels"); in mp3309c_parse_fwnode()
252 if (num_levels < 2) in mp3309c_parse_fwnode()
256 num_levels = MP3309C_PWM_DEFAULT_NUM_LEVELS; in mp3309c_parse_fwnode()
261 pdata->levels = devm_kcalloc(dev, num_levels, sizeof(*pdata->levels), GFP_KERNEL); in mp3309c_parse_fwnode()
266 pdata->levels, num_levels); in mp3309c_parse_fwnode()
270 for (i = 0; i < num_levels; i++) in mp3309c_parse_fwnode()
274 pdata->max_brightness = num_levels - 1; in mp3309c_parse_fwnode()
A Dpwm_bl.c222 unsigned int num_levels; in pwm_backlight_parse_dt() local
251 num_levels = length / sizeof(u32); in pwm_backlight_parse_dt()
254 if (num_levels > 0) { in pwm_backlight_parse_dt()
255 data->levels = devm_kcalloc(dev, num_levels, in pwm_backlight_parse_dt()
262 num_levels); in pwm_backlight_parse_dt()
287 unsigned int num_input_levels = num_levels; in pwm_backlight_parse_dt()
303 num_levels = (num_input_levels - 1) * num_steps + 1; in pwm_backlight_parse_dt()
305 num_levels); in pwm_backlight_parse_dt()
311 table = devm_kcalloc(dev, num_levels, sizeof(*table), in pwm_backlight_parse_dt()
344 data->max_brightness = num_levels - 1; in pwm_backlight_parse_dt()
/linux/drivers/firmware/arm_scmi/
A Dvoltage.c99 u32 num_levels; in scmi_init_voltage_levels() local
101 num_levels = num_returned + num_remaining; in scmi_init_voltage_levels()
106 if (!num_levels || in scmi_init_voltage_levels()
110 num_levels, num_returned, num_remaining, v->id); in scmi_init_voltage_levels()
114 v->levels_uv = devm_kcalloc(dev, num_levels, sizeof(u32), GFP_KERNEL); in scmi_init_voltage_levels()
118 v->num_levels = num_levels; in scmi_init_voltage_levels()
153 if (!p->v->num_levels) { in iter_volt_levels_update_state()
158 st->max_resources = p->v->num_levels; in iter_volt_levels_update_state()
196 iter = ph->hops->iter_response_init(ph, &ops, v->num_levels, in scmi_voltage_levels_get()
205 v->num_levels = 0; in scmi_voltage_levels_get()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c88 *num_levels = 2; in dcn3_init_single_clock()
92 *num_levels = ret & 0xFF; in dcn3_init_single_clock()
111 unsigned int num_levels; in dcn3_init_clocks() local
134 &num_levels); in dcn3_init_clocks()
140 &num_levels); in dcn3_init_clocks()
145 &num_levels); in dcn3_init_clocks()
151 &num_levels); in dcn3_init_clocks()
156 &num_levels); in dcn3_init_clocks()
161 &num_levels); in dcn3_init_clocks()
417 &num_levels); in dcn3_get_memclk_states_from_smu()
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/linux/fs/verity/
A Denable.c78 const int num_levels = params->num_levels; in build_merkle_tree() local
97 for (level = -1; level < num_levels; level++) { in build_merkle_tree()
104 buffers[num_levels].data = root_hash; in build_merkle_tree()
105 buffers[num_levels].is_root_hash = true; in build_merkle_tree()
132 for (level = 0; level < num_levels; level++) { in build_merkle_tree()
158 for (level = 0; level < num_levels; level++) { in build_merkle_tree()
172 if (WARN_ON_ONCE(buffers[num_levels].filled != params->digest_size)) { in build_merkle_tree()
178 for (level = -1; level < num_levels; level++) in build_merkle_tree()
A Dopen.c111 if (params->num_levels >= FS_VERITY_MAX_LEVELS) { in fsverity_init_merkle_tree_params()
118 blocks_in_level[params->num_levels++] = blocks; in fsverity_init_merkle_tree_params()
123 for (level = (int)params->num_levels - 1; level >= 0; level--) { in fsverity_init_merkle_tree_params()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
A Ddce112_resource.c1091 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1093 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1095 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1097 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1099 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1101 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1103 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1181 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; in bw_calcs_data_update_from_pplib()
1195 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; in bw_calcs_data_update_from_pplib()
1201 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; in bw_calcs_data_update_from_pplib()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce120/
A Ddce120_resource.c929 &eng_clks) || eng_clks.num_levels == 0) { in bw_calcs_data_update_from_pplib()
931 eng_clks.num_levels = 8; in bw_calcs_data_update_from_pplib()
934 for (i = 0; i < eng_clks.num_levels; i++) { in bw_calcs_data_update_from_pplib()
962 &mem_clks) || mem_clks.num_levels == 0) { in bw_calcs_data_update_from_pplib()
964 mem_clks.num_levels = 3; in bw_calcs_data_update_from_pplib()
968 for (i = 0; i < eng_clks.num_levels; i++) { in bw_calcs_data_update_from_pplib()
1008 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; in bw_calcs_data_update_from_pplib()
1012 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; in bw_calcs_data_update_from_pplib()
1026 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; in bw_calcs_data_update_from_pplib()
1032 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; in bw_calcs_data_update_from_pplib()
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/linux/arch/arm64/kernel/
A Dcacheinfo.c63 detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); in early_cache_level()
94 this_cpu_ci->num_levels = level; in init_cache_level()
106 for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/gpu/drm/radeon/
A Dsumo_dpm.c352 for (i = 0; i < ps->num_levels - 1; i++) in sumo_program_bsp()
406 for (i = 0; i < ps->num_levels; i++) { in sumo_program_at()
1109 for (i = 0; i < ps->num_levels; i++) { in sumo_apply_state_adjust_rules()
1142 else if (i == ps->num_levels - 1) in sumo_apply_state_adjust_rules()
1395 ps->num_levels = 1; in sumo_patch_boot_state()
1442 ps->num_levels = index + 1; in sumo_parse_pplib_clock_info()
1738 pi->current_ps.num_levels = 1; in sumo_construct_boot_and_acpi_state()
1805 for (i = 0; i < ps->num_levels; i++) { in sumo_dpm_print_power_state()
1929 if (ps->num_levels <= 1) in sumo_dpm_force_performance_level()
1950 for (i = 1; i < ps->num_levels; i++) { in sumo_dpm_force_performance_level()
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A Dtrinity_dpm.c1161 if (ps->num_levels <= 1) in trinity_dpm_force_performance_level()
1172 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_force_performance_level()
1280 ps->num_levels = 1; in trinity_patch_boot_state()
1305 pi->current_ps.num_levels = 1; in trinity_construct_boot_state()
1386 if (ps == NULL || ps->num_levels <= 1) in trinity_calculate_display_wm()
1388 else if (ps->num_levels == 2) { in trinity_calculate_display_wm()
1514 for (i = 0; i < ps->num_levels; i++) { in trinity_apply_state_adjust_rules()
1673 ps->num_levels = index + 1; in trinity_parse_pplib_clock_info()
1974 for (i = 0; i < ps->num_levels; i++) { in trinity_dpm_print_power_state()
1994 if (current_index >= ps->num_levels) { in trinity_dpm_debugfs_print_current_performance_level()
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A Dr100_track.h44 unsigned num_levels; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
A Ddcn32_clk_mgr.c133 unsigned int *num_levels) in dcn32_init_single_clock() argument
142 *num_levels = 2; in dcn32_init_single_clock()
146 *num_levels = ret & 0xFF; in dcn32_init_single_clock()
149 for (i = 0; i < *num_levels; i++) { in dcn32_init_single_clock()
165 unsigned int num_levels; in dcn32_init_clocks() local
237 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
243 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
248 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
255 for (i = 0; i < num_levels; i++) in dcn32_init_clocks()
1030 unsigned int num_levels; in dcn32_get_memclk_states_from_smu() local
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/linux/drivers/gpu/drm/amd/display/dc/
A Ddm_services_types.h98 uint32_t num_levels; member
108 uint32_t num_levels; member
118 uint32_t num_levels; member
/linux/drivers/gpu/drm/amd/include/
A Ddm_pp_interface.h174 uint32_t num_levels; member
184 uint32_t num_levels; member
/linux/drivers/gpu/drm/i915/display/
A Dintel_wm.c151 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { in intel_print_wm_latency()
191 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { in wm_latency_show()
309 if (ret != dev_priv->display.wm.num_levels) in wm_latency_write()
314 for (level = 0; level < dev_priv->display.wm.num_levels; level++) in wm_latency_write()
A Di9xx_wm.c1058 if (level >= dev_priv->display.wm.num_levels) in g4x_raw_crtc_wm_is_valid()
1648 wm_state->num_levels = dev_priv->display.wm.num_levels; in _vlv_compute_pipe_wm()
1684 wm_state->num_levels = level; in _vlv_compute_pipe_wm()
1873 intermediate->num_levels = min(optimal->num_levels, active->num_levels); in vlv_compute_intermediate_wm()
2625 i915->display.wm.num_levels = 5; in hsw_read_wm_latency()
2642 i915->display.wm.num_levels = 4; in snb_read_wm_latency()
2656 i915->display.wm.num_levels = 3; in ilk_read_wm_latency()
2971 int level, num_levels = dev_priv->display.wm.num_levels; in ilk_wm_merge() local
2972 int last_enabled_level = num_levels - 1; in ilk_wm_merge()
2983 for (level = 1; level < num_levels; level++) { in ilk_wm_merge()
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A Dskl_watermark.c373 for (level = i915->display.wm.num_levels - 1; in skl_crtc_can_enable_sagv()
3279 u16 wm[], int num_levels, int read_latency) in adjust_wm_latency() argument
3289 for (level = 1; level < num_levels; level++) { in adjust_wm_latency()
3291 for (i = level + 1; i < num_levels; i++) in adjust_wm_latency()
3294 num_levels = level; in adjust_wm_latency()
3307 for (level = 0; level < num_levels; level++) in adjust_wm_latency()
3323 int num_levels = i915->display.wm.num_levels; in mtl_read_wm_latency() local
3338 adjust_wm_latency(i915, wm, num_levels, 6); in mtl_read_wm_latency()
3343 int num_levels = i915->display.wm.num_levels; in skl_read_wm_latency() local
3381 i915->display.wm.num_levels = 6; in skl_setup_wm_latency()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
A Ddce110_resource.c1295 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1297 clks.clocks_in_khz[clks.num_levels/8], 1000); in bw_calcs_data_update_from_pplib()
1299 clks.clocks_in_khz[clks.num_levels*2/8], 1000); in bw_calcs_data_update_from_pplib()
1301 clks.clocks_in_khz[clks.num_levels*3/8], 1000); in bw_calcs_data_update_from_pplib()
1303 clks.clocks_in_khz[clks.num_levels*4/8], 1000); in bw_calcs_data_update_from_pplib()
1305 clks.clocks_in_khz[clks.num_levels*5/8], 1000); in bw_calcs_data_update_from_pplib()
1307 clks.clocks_in_khz[clks.num_levels*6/8], 1000); in bw_calcs_data_update_from_pplib()
1318 clks.clocks_in_khz[clks.num_levels-1], 1000); in bw_calcs_data_update_from_pplib()
1320 clks.clocks_in_khz[clks.num_levels>>1], 1000); in bw_calcs_data_update_from_pplib()
1333 clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, in bw_calcs_data_update_from_pplib()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
89 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; in determine_sclk_from_bounding_box()
/linux/arch/s390/kernel/
A Dcache.c142 this_cpu_ci->num_levels = level; in init_cache_level()
156 for (idx = 0, level = 0; level < this_cpu_ci->num_levels && in populate_cache_leaves()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu10_hwmgr.c1207 clocks->num_levels = 0; in smu10_get_clock_by_type_with_latency()
1210 clocks->data[clocks->num_levels].clocks_in_khz = in smu10_get_clock_by_type_with_latency()
1212 clocks->data[clocks->num_levels].latency_in_us = latency_required ? in smu10_get_clock_by_type_with_latency()
1216 clocks->num_levels++; in smu10_get_clock_by_type_with_latency()
1261 clocks->num_levels = 0; in smu10_get_clock_by_type_with_voltage()
1264 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; in smu10_get_clock_by_type_with_voltage()
1265 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; in smu10_get_clock_by_type_with_voltage()
1266 clocks->num_levels++; in smu10_get_clock_by_type_with_voltage()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
A Ddcn401_clk_mgr.c146 unsigned int *num_levels) in dcn401_init_single_clock() argument
155 *num_levels = 2; in dcn401_init_single_clock()
159 *num_levels = ret & 0xFF; in dcn401_init_single_clock()
162 for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { in dcn401_init_single_clock()
1513 unsigned int num_levels; in dcn401_get_memclk_states_from_smu() local
1542 num_levels = num_entries_per_clk->num_memclk_levels; in dcn401_get_memclk_states_from_smu()
1544 num_levels = num_entries_per_clk->num_fclk_levels; in dcn401_get_memclk_states_from_smu()
1547 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; in dcn401_get_memclk_states_from_smu()
1549 if (clk_mgr->dpm_present && !num_levels) in dcn401_get_memclk_states_from_smu()

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