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Searched refs:num_pipes (Results 1 – 25 of 74) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddisplay_rq_dlg_calc_32.c46 const unsigned int num_pipes, in dml32_rq_dlg_get_rq_reg() argument
141 num_pipes, pipe_idx); in dml32_rq_dlg_get_rq_reg()
210 const unsigned int num_pipes, in dml32_rq_dlg_get_dlg_reg() argument
307 for (k = 0; k < num_pipes; ++k) { in dml32_rq_dlg_get_dlg_reg()
312 for (i = 0; i < num_pipes; i++) { in dml32_rq_dlg_get_dlg_reg()
318 for (j = i; j < num_pipes; j++) { in dml32_rq_dlg_get_dlg_reg()
391 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
417 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
483 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
496 num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_32.h47 const unsigned int num_pipes,
67 const unsigned int num_pipes,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_rq_dlg_calc_31.c854 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1063 for (k = 0; k < num_pipes; ++k) { in dml_rq_dlg_get_dlg_params()
1068 for (i = 0; i < num_pipes; i++) { in dml_rq_dlg_get_dlg_params()
1074 for (j = i; j < num_pipes; j++) { in dml_rq_dlg_get_dlg_params()
1552 const unsigned int num_pipes, in dml31_rq_dlg_get_dlg_reg() argument
1564 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1566 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1567 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1568 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
1569 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); in dml31_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_31.h61 const unsigned int num_pipes,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddisplay_rq_dlg_calc_314.c939 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1150 for (k = 0; k < num_pipes; ++k) { in dml_rq_dlg_get_dlg_params()
1155 for (i = 0; i < num_pipes; i++) { in dml_rq_dlg_get_dlg_params()
1161 for (j = i; j < num_pipes; j++) { in dml_rq_dlg_get_dlg_params()
1640 const unsigned int num_pipes, in dml314_rq_dlg_get_dlg_reg() argument
1652 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1654 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1655 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1656 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
1657 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); in dml314_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_314.h62 const unsigned int num_pipes,
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
A Ddml21_wrapper.c127 int num_pipes; in dml21_calculate_rq_and_dlg_params() local
155 if (num_pipes <= 0) in dml21_calculate_rq_and_dlg_params()
159 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { in dml21_calculate_rq_and_dlg_params()
291 int num_pipes; in dml21_prepare_mcache_programming() local
317 mcache_config->num_pipes = pln_prog->num_dpps_required; in dml21_prepare_mcache_programming()
325 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || in dml21_prepare_mcache_programming()
330 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { in dml21_prepare_mcache_programming()
344 mcache_config->num_pipes = pln_prog->num_dpps_required; in dml21_prepare_mcache_programming()
347 for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) { in dml21_prepare_mcache_programming()
365 if (num_pipes <= 0 || dc_main_pipes[0]->stream == NULL || in dml21_prepare_mcache_programming()
[all …]
/linux/drivers/gpu/drm/tidss/
A Dtidss_kms.c121 u32 num_pipes = 0; in tidss_dispc_modeset_init() local
177 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
178 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
179 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
180 num_pipes++; in tidss_dispc_modeset_init()
184 crtc_mask = (1 << num_pipes) - 1; in tidss_dispc_modeset_init()
188 for (i = 0; i < num_pipes; ++i) { in tidss_dispc_modeset_init()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_rq_dlg_calc_30.c891 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1188 for (k = 0; k < num_pipes; ++k) { in dml_rq_dlg_get_dlg_params()
1193 for (i = 0; i < num_pipes; i++) { in dml_rq_dlg_get_dlg_params()
1199 for (j = i; j < num_pipes; j++) { in dml_rq_dlg_get_dlg_params()
1251 num_pipes, in dml_rq_dlg_get_dlg_params()
1255 num_pipes, in dml_rq_dlg_get_dlg_params()
1733 const unsigned int num_pipes, in dml30_rq_dlg_get_dlg_reg() argument
1748 num_pipes); in dml30_rq_dlg_get_dlg_reg()
1755 num_pipes); in dml30_rq_dlg_get_dlg_reg()
1758 num_pipes); in dml30_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_30.h61 const unsigned int num_pipes,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_rq_dlg_calc_21.c828 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
980 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
1062 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1146 num_pipes, in dml_rq_dlg_get_dlg_params()
1151 num_pipes, in dml_rq_dlg_get_dlg_params()
1646 const unsigned int num_pipes, in dml21_rq_dlg_get_dlg_reg() argument
1658 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml21_rq_dlg_get_dlg_reg()
1662 num_pipes); in dml21_rq_dlg_get_dlg_reg()
1670 num_pipes); in dml21_rq_dlg_get_dlg_reg()
1674 num_pipes); in dml21_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_21.h65 const unsigned int num_pipes,
/linux/drivers/gpu/drm/omapdrm/
A Domap_drv.c307 for (i = 0; i < priv->num_pipes; i++) { in omap_disconnect_pipelines()
318 priv->num_pipes = 0; in omap_disconnect_pipelines()
338 pipe = &priv->pipes[priv->num_pipes++]; in omap_connect_pipelines()
421 if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) { in omap_modeset_init()
428 plane_crtc_mask = (1 << priv->num_pipes) - 1; in omap_modeset_init()
431 enum drm_plane_type type = i < priv->num_pipes in omap_modeset_init()
450 for (i = 0; i < priv->num_pipes; i++) { in omap_modeset_init()
478 for (i = 0; i < priv->num_pipes; ++i) { in omap_modeset_init()
489 for (i = 0; i < priv->num_pipes; i++) { in omap_modeset_init()
513 priv->num_planes, priv->num_pipes); in omap_modeset_init()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_rq_dlg_calc_20.c48 const unsigned int num_pipes,
782 const unsigned int num_pipes, in dml20_rq_dlg_get_dlg_params() argument
934 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_params()
1097 num_pipes, in dml20_rq_dlg_get_dlg_params()
1101 num_pipes, in dml20_rq_dlg_get_dlg_params()
1537 const unsigned int num_pipes, in dml20_rq_dlg_get_dlg_reg() argument
1549 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_reg()
1552 num_pipes); in dml20_rq_dlg_get_dlg_reg()
1559 num_pipes); in dml20_rq_dlg_get_dlg_reg()
1562 num_pipes); in dml20_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_20v2.c48 const unsigned int num_pipes,
782 const unsigned int num_pipes, in dml20v2_rq_dlg_get_dlg_params() argument
934 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_params()
1098 num_pipes, in dml20v2_rq_dlg_get_dlg_params()
1102 num_pipes, in dml20v2_rq_dlg_get_dlg_params()
1538 const unsigned int num_pipes, in dml20v2_rq_dlg_get_dlg_reg() argument
1550 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
1553 num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
1560 num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
1563 num_pipes); in dml20v2_rq_dlg_get_dlg_reg()
[all …]
A Ddisplay_rq_dlg_calc_20v2.h65 const unsigned int num_pipes,
A Ddisplay_rq_dlg_calc_20.h65 const unsigned int num_pipes,
/linux/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_lib.h56 const unsigned int num_pipes,
74 const unsigned int num_pipes,
79 const unsigned int num_pipes,
A Ddisplay_mode_vba.c47 unsigned int num_pipes);
55 unsigned int num_pipes) in dml_get_voltage_level() argument
59 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
66 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
84 recalculate_params(mode_lib, pipes, num_pipes); \
210 unsigned int num_pipes) in get_total_immediate_flip_bytes() argument
219 unsigned int num_pipes) in get_total_immediate_flip_bw() argument
232 unsigned int num_pipes) in get_total_prefetch_bw() argument
246 unsigned int num_pipes) in get_total_surface_size_in_mall_bytes() argument
960 unsigned int num_pipes) in recalculate_params() argument
[all …]
A Ddisplay_mode_vba.h34 …struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
75 …de_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int wh…
151 unsigned int num_pipes);
155 unsigned int num_pipes);
159 unsigned int num_pipes);
163 unsigned int num_pipes);
168 unsigned int num_pipes);
172 unsigned int num_pipes,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.h92 int num_pipes, struct dc_crtc_timing_adjust adjust);
95 int num_pipes, const struct dc_static_screen_params *params);
98 int num_pipes, uint32_t v_total_min, uint32_t v_total_max);
/linux/drivers/gpu/drm/radeon/
A Dr420.c94 unsigned num_pipes; in r420_pipes_init() local
105 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; in r420_pipes_init()
110 num_pipes = 1; in r420_pipes_init()
112 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
114 switch (num_pipes) { in r420_pipes_init()
117 num_pipes = 1; in r420_pipes_init()
132 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); in r420_pipes_init()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
A Ddcn10_hwseq.h146 int num_pipes, struct dc_crtc_timing_adjust adjust);
148 int num_pipes,
151 int num_pipes, const struct dc_static_screen_params *params);
/linux/include/drm/intel/
A Dintel_lpe_audio.h45 int num_pipes; member
/linux/drivers/gpu/drm/amd/display/dc/hwss/
A Dhw_sequencer.h255 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
274 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
277 int num_pipes,
461 …void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t …

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