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Searched refs:opp_cnt (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
A Ddcn314_hwseq.c77 int opp_cnt = 1; in update_dsc_on_stream() local
81 opp_cnt++; in update_dsc_on_stream()
96 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
108 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
161 int opp_cnt = 0; in dcn314_update_odm() local
168 if (opp_cnt > 1) in dcn314_update_odm()
171 opp_inst, opp_cnt, in dcn314_update_odm()
391 int opp_cnt = 1; in dcn314_resync_fifo_dccg_dio() local
398 opp_cnt++; in dcn314_resync_fifo_dccg_dio()
400 if (opp_cnt > 1) in dcn314_resync_fifo_dccg_dio()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
A Ddcn314_optc.c50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc314_set_odm_combine() argument
55 int h_active = segment_width * opp_cnt; in optc314_set_odm_combine()
64 if (opp_cnt == 4) { in optc314_set_odm_combine()
83 if (opp_cnt == 2) { in optc314_set_odm_combine()
88 } else if (opp_cnt == 4) { in optc314_set_odm_combine()
101 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine()
102 optc1->opp_count = opp_cnt; in optc314_set_odm_combine()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/
A Ddcn30_optc.c218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
232 ASSERT(opp_cnt == 2 || opp_cnt == 4); in optc3_set_odm_combine()
237 if (opp_cnt == 2) { in optc3_set_odm_combine()
242 } else if (opp_cnt == 4) { in optc3_set_odm_combine()
253 if (opp_cnt == 2) { in optc3_set_odm_combine()
258 } else if (opp_cnt == 4) { in optc3_set_odm_combine()
270 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
271 optc1->opp_count = opp_cnt; in optc3_set_odm_combine()
A Ddcn30_optc.h354 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn32/
A Ddcn32_optc.c45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc32_set_odm_combine() argument
50 int h_active = segment_width * opp_cnt; in optc32_set_odm_combine()
59 if (opp_cnt == 4) { in optc32_set_odm_combine()
78 if (opp_cnt == 2) { in optc32_set_odm_combine()
83 } else if (opp_cnt == 4) { in optc32_set_odm_combine()
96 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
97 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
A Ddcn31_optc.c43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc31_set_odm_combine() argument
51 if (opp_cnt == 4) { in optc31_set_odm_combine()
71 if (opp_cnt == 2) { in optc31_set_odm_combine()
76 } else if (opp_cnt == 4) { in optc31_set_odm_combine()
88 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
89 optc1->opp_count = opp_cnt; in optc31_set_odm_combine()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
A Ddcn401_optc.c57 static uint32_t decide_odm_mem_bit_map(int *opp_id, int opp_cnt, int h_active) in decide_odm_mem_bit_map() argument
66 for (i = 0; i < opp_cnt; i++) { in decide_odm_mem_bit_map()
74 for (i = 0; i < opp_cnt; i++) { in decide_odm_mem_bit_map()
105 int opp_cnt, int segment_width, int last_segment_width) in optc401_set_odm_combine() argument
108 uint32_t h_active = segment_width * (opp_cnt - 1) + last_segment_width; in optc401_set_odm_combine()
110 opp_id, opp_cnt, h_active); in optc401_set_odm_combine()
115 switch (opp_cnt) { in optc401_set_odm_combine()
162 optc1->opp_count = opp_cnt; in optc401_set_odm_combine()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/
A Ddcn35_optc.c58 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc35_set_odm_combine() argument
63 int h_active = segment_width * opp_cnt; in optc35_set_odm_combine()
72 if (opp_cnt == 4) { in optc35_set_odm_combine()
91 if (opp_cnt == 2) { in optc35_set_odm_combine()
96 } else if (opp_cnt == 4) { in optc35_set_odm_combine()
108 REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc35_set_odm_combine()
109 optc1->opp_count = opp_cnt; in optc35_set_odm_combine()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
A Ddcn32_hwseq.c1013 int opp_cnt = 1; in dcn32_update_dsc_on_stream() local
1029 opp_cnt++; in dcn32_update_dsc_on_stream()
1125 int opp_cnt = 0; in dcn32_update_odm() local
1132 if (opp_cnt > 1) in dcn32_update_odm()
1135 opp_inst, opp_cnt, in dcn32_update_odm()
1269 int opp_cnt = 1; in dcn32_resync_fifo_dccg_dio() local
1276 opp_cnt++; in dcn32_resync_fifo_dccg_dio()
1278 if (opp_cnt > 1) in dcn32_resync_fifo_dccg_dio()
1281 opp_inst, opp_cnt, in dcn32_resync_fifo_dccg_dio()
1300 params.opp_cnt = 1; in dcn32_unblank_stream()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
A Ddcn20_optc.c181 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
187 ASSERT(opp_cnt == 2); in optc2_set_odm_combine()
217 optc1->opp_count = opp_cnt; in optc2_set_odm_combine()
A Ddcn20_optc.h107 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
A Ddcn35_hwseq.c325 int opp_cnt = 1; in update_dsc_on_stream() local
331 opp_cnt++; in update_dsc_on_stream()
352 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in update_dsc_on_stream()
358 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
359 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
370 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
371 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
424 int opp_cnt = 0; in dcn35_update_odm() local
429 opp_cnt = get_odm_config(pipe_ctx, opp_inst); in dcn35_update_odm()
431 if (opp_cnt > 1) in dcn35_update_odm()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
A Ddcn20_hwseq.c766 if (opp_cnt >= 2) in calc_mpc_flow_ctrl_cnt()
777 if (opp_cnt == 4) in calc_mpc_flow_ctrl_cnt()
823 int opp_cnt = 1; in dcn20_enable_stream_timing() local
853 for (i = 0; i < opp_cnt; i++) in dcn20_enable_stream_timing()
858 if (opp_cnt > 1) in dcn20_enable_stream_timing()
1179 int opp_cnt = 1; in dcn20_update_odm() local
1186 opp_cnt++; in dcn20_update_odm()
1189 if (opp_cnt > 1) in dcn20_update_odm()
1192 opp_inst, opp_cnt, in dcn20_update_odm()
2729 params.opp_cnt = 1; in dcn20_unblank_stream()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
A Ddcn401_hwseq.c771 int *opp_cnt, in enable_stream_timing_calc() argument
783 *opp_cnt = resource_get_opp_heads_for_otg_master(pipe_ctx, &context->res_ctx, opp_heads); in enable_stream_timing_calc()
784 for (i = 0; i < *opp_cnt; i++) in enable_stream_timing_calc()
814 int opp_cnt = 1; in dcn401_enable_stream_timing() local
828 &opp_cnt, opp_heads, &manual_mode, &params, &event_triggers); in dcn401_enable_stream_timing()
838 if (opp_cnt > 1) { in dcn401_enable_stream_timing()
843 opp_inst, opp_cnt, in dcn401_enable_stream_timing()
875 for (i = 0; i < opp_cnt; i++) { in dcn401_enable_stream_timing()
1635 params.opp_cnt = resource_get_odm_slice_count(pipe_ctx); in dcn401_unblank_stream()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
A Ddcn20_resource.c1222 int opp_cnt = 1; in get_pixel_clock_parameters() local
1229 opp_cnt++; in get_pixel_clock_parameters()
1252 if (opp_cnt == 4) in get_pixel_clock_parameters()
1254 …else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt =… in get_pixel_clock_parameters()
1268 opp_cnt > 1) { in get_pixel_clock_parameters()
1682 int opp_cnt = 1; in dcn20_validate_dsc() local
1685 opp_cnt++; in dcn20_validate_dsc()
1692 + stream->timing.h_border_right) / opp_cnt; in dcn20_validate_dsc()
1699 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
/linux/drivers/gpu/drm/amd/display/dc/link/
A Dlink_dpms.c787 int opp_cnt = 1; in link_set_dsc_on_stream() local
803 opp_cnt++; in link_set_dsc_on_stream()
811 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in link_set_dsc_on_stream()
817 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in link_set_dsc_on_stream()
818 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in link_set_dsc_on_stream()
832 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in link_set_dsc_on_stream()
833 dsc_cfg.pic_width *= opp_cnt; in link_set_dsc_on_stream()
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dstream_encoder.h101 int opp_cnt; member
A Dtiming_generator.h317 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/
A Ddcn314_dio_stream_encoder.c303 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) { in enc314_stream_encoder_dp_unblank()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_stream_encoder.c259 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1 in enc32_stream_encoder_dp_unblank()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_stream_encoder.c291 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1 in enc35_stream_encoder_dp_unblank()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_stream_encoder.c482 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) { in enc2_stream_encoder_dp_unblank()

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