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Searched refs:performance_level_count (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/radeon/
A Dni_dpm.c833 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
863 for (i = 1; i < ps->performance_level_count; i++) in ni_apply_state_adjust_rules()
868 for (i = 0; i < ps->performance_level_count; i++) in ni_apply_state_adjust_rules()
872 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
887 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
1397 if (state->performance_level_count < 3) in ni_calculate_power_boost_limit()
2406 if (state->performance_level_count >= 9) in ni_populate_smc_t()
2409 if (state->performance_level_count < 2) { in ni_populate_smc_t()
2474 if (state->performance_level_count == 0) in ni_populate_power_containment_values()
2551 if (state->performance_level_count == 0) in ni_populate_sq_ramping_values()
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A Dsi_dpm.c2244 if (state->performance_level_count == 0) in si_populate_power_containment_values()
2326 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()
2992 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3084 for (i = 0; i < ps->performance_level_count; i++) in si_apply_state_adjust_rules()
3088 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3105 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3342 u32 levels = ps->performance_level_count; in si_dpm_force_performance_level()
5034 if (state->performance_level_count >= 9) in si_populate_smc_t()
5037 if (state->performance_level_count < 2) { in si_populate_smc_t()
5216 new_state->performance_level_count); in si_upload_sw_state()
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A Dni_dpm.h169 u16 performance_level_count; member
A Dci_dpm.h47 u16 performance_level_count; member
A Dci_dpm.c800 for (i = 0; i < ps->performance_level_count; i++) { in ci_apply_state_adjust_rules()
811 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()
3712 if (state->performance_level_count < 1) in ci_trim_dpm_states()
3715 if (state->performance_level_count == 1) in ci_trim_dpm_states()
3817 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_find_dpm_states_clocks_in_dpm_table()
3819 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table()
3858 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3859 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4760 for (i = 0; i < state->performance_level_count; i++) { in ci_get_maximum_link_speed()
5438 ps->performance_level_count = index + 1; in ci_parse_pplib_clock_info()
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/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dsi_dpm.c2402 if (state->performance_level_count == 0) in si_populate_power_containment_values()
2483 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()
3601 for (i = 0; i < ps->performance_level_count; i++) in si_apply_state_adjust_rules()
3860 u32 levels = ps->performance_level_count; in si_dpm_force_performance_level()
5576 if (state->performance_level_count >= 9) in si_populate_smc_t()
5579 if (state->performance_level_count < 2) { in si_populate_smc_t()
5758 new_state->performance_level_count); in si_upload_sw_state()
7187 ps->performance_level_count = index + 1; in si_parse_pplib_clock_info()
7976 if (si_cps->performance_level_count != si_rps->performance_level_count) { in si_check_state_equal()
8014 if (pl_index < ps->performance_level_count) { in si_dpm_read_sensor()
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A Dsi_dpm.h622 u16 performance_level_count; member
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu7_hwmgr.c3409 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules()
3506 [smu7_ps->performance_level_count-1].memory_clock; in smu7_dpm_get_mclk()
3642 [smu7_power_state->performance_level_count++]); in smu7_get_pp_table_entry_callback_func_v1()
3650 (smu7_power_state->performance_level_count < in smu7_get_pp_table_entry_callback_func_v1()
3670 [smu7_power_state->performance_level_count++]); in smu7_get_pp_table_entry_callback_func_v1()
3814 (ps->performance_level_count < in smu7_get_pp_table_entry_callback_func_v0()
3820 [ps->performance_level_count++]); in smu7_get_pp_table_entry_callback_func_v0()
4730 if (psa->performance_level_count != psb->performance_level_count) { in smu7_check_states_equal()
4735 for (i = 0; i < psa->performance_level_count; i++) { in smu7_check_states_equal()
5722 i = index > ps->performance_level_count - 1 ? in smu7_get_performance_level()
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A Dvega10_hwmgr.c3190 [vega10_ps->performance_level_count++]); in vega10_get_pp_table_entry_callback_func()
3193 (vega10_ps->performance_level_count < in vega10_get_pp_table_entry_callback_func()
3199 (vega10_ps->performance_level_count < in vega10_get_pp_table_entry_callback_func()
3214 [vega10_ps->performance_level_count++]); in vega10_get_pp_table_entry_callback_func()
3306 if (vega10_ps->performance_level_count != 2) in vega10_apply_state_adjust_rules()
3925 [vega10_ps->performance_level_count-1].mem_clock; in vega10_dpm_get_mclk()
5049 if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) { in vega10_check_states_equal()
5182 [vega10_ps->performance_level_count - 1].gfx_clock = in vega10_set_sclk_od()
5477 max_level = vega10_ps->performance_level_count - 1; in vega10_odn_update_power_state()
5502 max_level = vega10_ps->performance_level_count - 1; in vega10_odn_update_power_state()
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A Dsmu7_hwmgr.h82 uint16_t performance_level_count; member
A Dvega10_hwmgr.h109 uint16_t performance_level_count; member
A Dvega20_hwmgr.h126 uint16_t performance_level_count; member

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