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Searched refs:phy_clear_bits (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/net/phy/
A Dnxp-cbtx.c40 ret = phy_clear_bits(phydev, CBTX_PDOWN_CTRL, in cbtx_soft_reset()
92 ret = phy_clear_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
97 return phy_clear_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
100 ret = phy_clear_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
A Dadin.c371 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2, in adin_set_downshift()
415 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2, in adin_set_edpd()
577 err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG, in adin_phy_config_intr()
708 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN); in adin_config_aneg()
890 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN); in adin_cable_test_start()
894 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN); in adin_cable_test_start()
A Dnxp-tja11xx.c140 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); in tja11xx_disable_link_control()
159 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); in tja11xx_wakeup()
339 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM); in tja11xx_config_init()
720 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_cable_test_start()
A Dmxl-gpy.c754 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL); in gpy_set_wol()
781 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); in gpy_set_wol()
A Ddp83867.c444 return phy_clear_bits(phydev, DP83867_CFG2, in dp83867_set_downshift()
1002 val = phy_clear_bits(phydev, DP83867_CFG2, in dp83867_link_change_notify()
A Dbroadcom.c194 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
205 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
A Dsmsc.c97 return phy_clear_bits(phydev, MII_LAN83C185_CTRL_STATUS, in smsc_phy_config_edpd()
A Dmarvell.c1055 err = phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR, in m88e1111_set_downshift()
1119 err = phy_clear_bits(phydev, MII_M1011_PHY_SCR, in m88e1011_set_downshift()
1514 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
2292 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE); in marvell_cable_test_start_common()
A Ddp83869.c443 return phy_clear_bits(phydev, DP83869_CFG2, in dp83869_set_downshift()
A Dmicrel.c779 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST); in ksz8081_config_init()
1868 ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL, in ksz886x_config_aneg()
2259 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100); in ksz886x_cable_test_start()
A Dphy_device.c2905 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in genphy_resume()
/linux/drivers/net/ethernet/realtek/
A Dr8169_phy_config.c500 phy_clear_bits(phydev, 0x03, 0xe000); in rtl8168d_1_hw_phy_config()
521 phy_clear_bits(phydev, 0x03, 0xe000); in rtl8168d_2_hw_phy_config()
718 phy_clear_bits(phydev, 0x19, BIT(0)); in rtl8411_hw_phy_config()
719 phy_clear_bits(phydev, 0x10, BIT(10)); in rtl8411_hw_phy_config()
/linux/drivers/net/phy/qcom/
A Dqca807x.c671 ret = phy_clear_bits(phydev, in qca807x_sfp_insert()
/linux/include/linux/
A Dphy.h1483 static inline int phy_clear_bits(struct phy_device *phydev, u32 regnum, u16 val) in phy_clear_bits() function

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