| /linux/drivers/net/ethernet/realtek/ |
| A D | r8169_phy_config.c | 286 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168bb_hw_phy_config()
307 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168cp_2_hw_phy_config()
308 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168cp_2_hw_phy_config()
337 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_1_hw_phy_config()
338 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168c_1_hw_phy_config()
364 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168c_2_hw_phy_config()
365 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_2_hw_phy_config()
366 phy_set_bits(phydev, 0x0d, BIT(5)); in rtl8168c_2_hw_phy_config()
386 phy_set_bits(phydev, 0x16, BIT(0)); in rtl8168c_3_hw_phy_config()
387 phy_set_bits(phydev, 0x14, BIT(5)); in rtl8168c_3_hw_phy_config()
[all …]
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| /linux/drivers/net/phy/ |
| A D | nxp-tja11xx.c | 130 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN); in tja11xx_enable_reg_write()
135 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL); in tja11xx_enable_link_control()
155 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST); in tja11xx_wakeup()
331 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_config_init()
732 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST); in tja11xx_cable_test_start()
793 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP); in tja11xx_cable_test_get_status()
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| A D | nxp-cbtx.c | 89 return phy_set_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
105 return phy_set_bits(phydev, CBTX_MODE_CTRL_STAT, in cbtx_mdix_config()
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| A D | mediatek-ge.c | 58 phy_set_bits(phydev, 0x17, BIT(4)); in mt7531_phy_config_init()
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| A D | adin.c | 385 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2, in adin_set_downshift()
574 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG, in adin_phy_config_intr()
712 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN); in adin_config_aneg()
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| A D | smsc.c | 94 return phy_set_bits(phydev, MII_LAN83C185_CTRL_STATUS, in smsc_phy_config_edpd()
194 int rc = phy_set_bits(phydev, PHY_EDPD_CONFIG, in lan95xx_config_aneg_ext()
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| A D | icplus.c | 281 ret = phy_set_bits(phydev, IP10XX_SPEC_CTRL_STATUS, IP101A_G_APS_ON); in ip101a_config_init()
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| A D | realtek.c | 366 return phy_set_bits(phydev, MII_CTRL1000, in rtl8211c_config_init()
652 ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE, in rtl8366rb_config_init()
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| A D | mxl-gpy.c | 763 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC); in gpy_set_wol()
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| A D | dp83867.c | 1007 phy_set_bits(phydev, DP83867_CFG2, in dp83867_link_change_notify()
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| A D | bcm-phy-lib.c | 637 return phy_set_bits(phydev, MII_BCM54XX_ECR, MII_BCM54XX_ECR_FIFOE); in bcm_phy_enable_jumbo()
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| A D | broadcom.c | 180 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
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| A D | marvell.c | 1298 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1, in m88e1510_config_init()
1542 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
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| A D | micrel.c | 1373 return phy_set_bits(phydev, 0x1e, BIT(9)); in ksz9131_led_errata()
1859 ret = phy_set_bits(phydev, MII_KSZPHY_CTRL, in ksz886x_config_aneg()
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| A D | phy_device.c | 2899 return phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in genphy_suspend()
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| /linux/drivers/net/phy/qcom/ |
| A D | qca83xx.c | 123 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); in qca83xx_config_init()
167 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); in qca83xx_resume()
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| A D | qca807x.c | 690 phy_set_bits(phydev, in qca807x_sfp_remove()
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| A D | at803x.c | 908 err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value); in at8031_config_intr()
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| /linux/include/linux/ |
| A D | phy.h | 1472 static inline int phy_set_bits(struct phy_device *phydev, u32 regnum, u16 val) in phy_set_bits() function
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