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Searched refs:phy_write_mmd (Results 1 – 25 of 40) sorted by relevance

12

/linux/drivers/net/phy/qcom/
A Dqca808x.c117 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, in qca808x_phy_fast_retrain_config()
119 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, in qca808x_phy_fast_retrain_config()
121 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, in qca808x_phy_fast_retrain_config()
123 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, in qca808x_phy_fast_retrain_config()
218 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in qca808x_config_init()
348 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); in qca808x_cable_test_start()
349 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); in qca808x_cable_test_start()
350 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); in qca808x_cable_test_start()
351 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); in qca808x_cable_test_start()
352 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); in qca808x_cable_test_start()
[all …]
A Dqca83xx.c112 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); in qca83xx_config_init()
115 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); in qca83xx_config_init()
/linux/drivers/net/phy/
A Dmarvell-88q2xxx.c182 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_soft_reset()
479 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
488 return phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
492 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
497 return phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
714 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x48); in mv88q222x_soft_reset()
724 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffe4, 0xc); in mv88q222x_soft_reset()
741 ret = phy_write_mmd(phydev, vals->devad, vals->regnum, in mv88q222x_write_mmd_vals()
805 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q222x_cable_test_start()
810 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q222x_cable_test_start()
[all …]
A Dmediatek-ge.c37 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); in mtk_gephy_config_init()
40 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); in mtk_gephy_config_init()
62 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); in mt7531_phy_config_init()
63 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); in mt7531_phy_config_init()
A Dnxp-c45-tja11xx.c451 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
459 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
553 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
635 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_hwtxts()
741 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
1037 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1042 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1276 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_handle_interrupt()
1418 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_init()
1741 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
[all …]
A Ddp83tg720.c97 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2, in dp83tg720_cable_test_start()
102 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3, in dp83tg720_cable_test_start()
107 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG4, in dp83tg720_cable_test_start()
112 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_0405, in dp83tg720_cable_test_start()
117 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_083F, in dp83tg720_cable_test_start()
333 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LPS_CFG3, in dp83tg720_config_init()
A Dintel-xway.c255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_config_init()
259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_config_init()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_config_init()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_config_init()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_config_init()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_config_init()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_config_init()
277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_config_init()
A Ddp83869.c273 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
279 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
285 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
297 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
303 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
308 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
706 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, in dp83869_configure_mode()
741 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
753 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
774 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
[all …]
A Ddp83tc811.c113 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1, in dp83811_set_wol()
115 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2, in dp83811_set_wol()
117 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3, in dp83811_set_wol()
128 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
131 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
134 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
148 return phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
A Dmediatek-ge-soc.c522 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); in tx_r50_fill_result()
769 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); in mt7981_phy_finetune()
806 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); in mt7981_phy_finetune()
808 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); in mt7981_phy_finetune()
810 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); in mt7981_phy_finetune()
812 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); in mt7981_phy_finetune()
814 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); in mt7981_phy_finetune()
838 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); in mt7988_phy_finetune()
841 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); in mt7988_phy_finetune()
1171 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mt798x_phy_hw_led_blink_set()
[all …]
A Ddp83td510.c185 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
197 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
389 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2, in dp83td510_cable_test_start()
397 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_FAULT_CFG1, in dp83td510_cable_test_start()
408 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_UNKN_030E, in dp83td510_cable_test_start()
413 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3, in dp83td510_cable_test_start()
A Dmicrel.c1068 return phy_write_mmd(phydev, 2, reg, newval); in ksz9031_of_load_skew_values()
1310 return phy_write_mmd(phydev, 2, reg, newval); in ksz9131_of_load_skew_values()
4074 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
4077 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
4087 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
4101 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
4106 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, in lan8841_config_init()
4108 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG, in lan8841_config_init()
4616 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_settime64()
4646 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_gettime64()
[all …]
A Dmicrochip_t1s.c99 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb0_indirect_read()
104 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, in lan865x_revb0_indirect_read()
153 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_write_cfg_params()
204 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb0_config_init()
A Dsmsc.c280 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_phy_config_init()
286 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_MCFGR, in lan874x_phy_config_init()
376 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
382 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
390 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, *mask); in lan874x_set_wol_pattern()
400 phy_write_mmd(phydev, MDIO_MMD_PCS, reg, 0); in lan874x_set_wol_pattern()
486 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, in lan874x_set_wol()
493 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_set_wol()
A Dbcm87xx.c69 ret = phy_write_mmd(phydev, devid, reg, val); in bcm87xx_of_reg_init()
155 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
159 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
A Ddp83822.c162 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1, in dp83822_config_wol()
164 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2, in dp83822_config_wol()
166 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3, in dp83822_config_wol()
177 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_config_wol()
180 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_config_wol()
183 phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_config_wol()
197 return phy_write_mmd(phydev, DP83822_DEVADDR, in dp83822_config_wol()
762 phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value | in dp83822_resume()
A Ddp83867.c230 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, in dp83867_set_wol()
232 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, in dp83867_set_wol()
234 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, in dp83867_set_wol()
243 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, in dp83867_set_wol()
245 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, in dp83867_set_wol()
247 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, in dp83867_set_wol()
269 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); in dp83867_set_wol()
858 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init()
867 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, in dp83867_config_init()
912 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); in dp83867_config_init()
[all …]
A Dair_en8811h.c579 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_blink_set()
715 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), in air_led_hw_control_set()
752 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, in air_leds_init()
757 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, in air_leds_init()
871 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, in en8811h_config_init()
875 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, in en8811h_config_init()
879 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_config_init()
883 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_config_init()
1027 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_clear_intr()
1032 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_clear_intr()
A Dmarvell-88x2222.c78 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
199 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
A Dmicrochip_t1.c1259 ret = phy_write_mmd(phydev, reg_map[i].mmd, in lan887x_phy_config()
1381 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST, in lan887x_phy_reset()
1484 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST, in lan887x_cd_reset()
1539 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in lan887x_cable_test_prep()
1544 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038); in lan887x_cable_test_prep()
1555 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg, in lan887x_cable_test_prep()
1562 rc = phy_write_mmd(phydev, values[i].mmd, in lan887x_cable_test_prep()
1591 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_prep()
1626 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_chk()
1797 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_report()
A Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
A Dphy-c45.c167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
1383 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1391 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1423 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
/linux/drivers/net/phy/aquantia/
A Daquantia_firmware.c96 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
99 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
102 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
116 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5, in aqr_fw_load_memory()
118 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6, in aqr_fw_load_memory()
121 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1, in aqr_fw_load_memory()
262 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
284 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
290 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
A Daquantia_hwmon.c65 return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp); in aqr_hwmon_set()
/linux/rust/kernel/net/phy/
A Dreg.rs212 bindings::phy_write_mmd(phydev, self.devad.0.into(), self.regnum.into(), val) in write()

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