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Searched refs:phydev_dbg (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/net/phy/
A Dnxp-c45-tja11xx-macsec.c721 phydev_dbg(phydev, "encryption %s\n", in nxp_c45_tx_sc_update()
728 phydev_dbg(phydev, "protect frames %s\n", in nxp_c45_tx_sc_update()
735 phydev_dbg(phydev, "send sci %s\n", in nxp_c45_tx_sc_update()
742 phydev_dbg(phydev, "end station %s\n", in nxp_c45_tx_sc_update()
749 phydev_dbg(phydev, "scb %s\n", in nxp_c45_tx_sc_update()
824 phydev_dbg(phydev, "validate frames %u\n", in nxp_c45_rx_sc_update()
837 phydev_dbg(phydev, "rx_sc->active %s\n", in nxp_c45_rx_sc_update()
985 phydev_dbg(phydev, "add SecY SCI %016llx\n", in nxp_c45_mdo_add_secy()
1053 phydev_dbg(phydev, "update SecY SCI %016llx\n", in nxp_c45_mdo_upd_secy()
1092 phydev_dbg(phydev, "delete SecY SCI %016llx\n", in nxp_c45_mdo_del_secy()
[all …]
A Dmeson-gxl.c178 phydev_dbg(phydev, "LPA corruption - aneg restart\n"); in meson_gxl_read_status()
A Dadin1100.c256 phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n", in adin_get_features()
A Dnxp-c45-tja11xx.c1516 phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret); in nxp_c45_set_phy_mode()
1651 phydev_dbg(phydev, "the phy does not support PTP"); in nxp_c45_probe()
1667 phydev_dbg(phydev, "PTP support not enabled even if the phy supports it"); in nxp_c45_probe()
1679 phydev_dbg(phydev, "MACsec support enabled."); in nxp_c45_probe()
1681 phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it"); in nxp_c45_probe()
A Dmediatek-ge-soc.c355 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); in cal_cycle()
619 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); in tx_vcm_cal_sw()
678 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); in tx_vcm_cal_sw()
A Dsmsc.c458 phydev_dbg(phydev, "pattern not valid at %d\n", rc); in lan874x_set_wol()
A Ddp83822.c675 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); in dp83822_read_straps()
A Dbcm54140.c606 phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n", in bcm54140_probe()
A Dadin.c551 phydev_dbg(phydev, "PHY is using mode '%s'\n", in adin_config_init()
A Dmotorcomm.c2799 phydev_dbg(phydev, in yt8821_read_status()
2805 phydev_dbg(phydev, in yt8821_read_status()
A Dphy.c65 phydev_dbg(phydev, "PHY state change %s -> %s\n", in phy_process_state_change()
A Dmicrel.c3846 phydev_dbg(phydev, "successfully registered ptp clock\n"); in lan8814_ptp_probe_once()
/linux/drivers/net/phy/aquantia/
A Daquantia_firmware.c244 phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n", in aqr_fw_boot()
265 phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n", in aqr_fw_boot()
272 phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n", in aqr_fw_boot()
A Daquantia_main.c484 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", in aqr107_chip_info()
573 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", in aqr107_link_change_notify()
/linux/drivers/net/phy/qcom/
A Dat803x.c504 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); in at803x_link_change_notify()
/linux/include/linux/
A Dphy.h1857 #define phydev_dbg(_phydev, format, args...) \ macro

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