| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_dp.h | 39 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
98 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
147 u32 pipe_bpp,
178 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
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| A D | intel_dp.c | 899 u32 pipe_bpp, in intel_dp_dsc_get_max_compressed_bpp() argument
1362 int pipe_bpp; in intel_dp_mode_valid() local
2017 int pipe_bpp, in icl_dsc_compute_link_config() argument
2059 int pipe_bpp, in xelpd_dsc_compute_link_config() argument
2104 int pipe_bpp, in dsc_compute_compressed_bpp() argument
2121 pipe_bpp / 3); in dsc_compute_compressed_bpp()
2148 int pipe_bpp) in is_dsc_pipe_bpp_sufficient() argument
2237 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_pipe_bpp()
2283 pipe_bpp / 3); in intel_edp_dsc_compute_pipe_bpp()
2293 pipe_config->pipe_bpp = pipe_bpp; in intel_edp_dsc_compute_pipe_bpp()
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| A D | intel_fdi.c | 308 int pipe_bpp = min(crtc_state->pipe_bpp, in intel_fdi_compute_pipe_bpp() local
311 pipe_bpp = rounddown(pipe_bpp, 2 * 3); in intel_fdi_compute_pipe_bpp()
313 if (pipe_bpp < 6 * 3) in intel_fdi_compute_pipe_bpp()
316 crtc_state->pipe_bpp = pipe_bpp; in intel_fdi_compute_pipe_bpp()
341 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
345 intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp), in ilk_fdi_compute_config()
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| A D | g4x_hdmi.c | 46 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
308 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
351 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
362 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
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| A D | intel_lvds.c | 298 if (crtc_state->dither && crtc_state->pipe_bpp == 18) in intel_pre_enable_lvds()
443 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { in intel_lvds_compute_config()
446 crtc_state->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
447 crtc_state->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
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| A D | intel_dp_mst.c | 308 crtc_state->pipe_bpp = bpp; in intel_dp_mst_find_vcpi_slots_for_bpp()
389 crtc_state->pipe_bpp = max_bpp; in intel_dp_dsc_mst_compute_link_config()
406 crtc_state->pipe_bpp); in intel_dp_dsc_mst_compute_link_config()
408 crtc_state->pipe_bpp); in intel_dp_dsc_mst_compute_link_config()
560 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24); in intel_dp_mst_compute_config_limits()
1509 int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX); in intel_dp_mst_mode_valid_ctx() local
1520 pipe_bpp, 64); in intel_dp_mst_mode_valid_ctx()
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| A D | intel_link_bw.c | 99 link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp); in intel_link_bw_reduce_bpp()
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| A D | intel_display.c | 3076 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
3079 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
3082 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
3452 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
3455 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
3458 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
3461 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
4375 crtc_state->pipe_bpp); in compute_sink_pipe_bpp()
4377 crtc_state->pipe_bpp = bpp; in compute_sink_pipe_bpp()
4402 crtc_state->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
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| A D | intel_hdmi.c | 938 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
943 switch (pipe_bpp) { in gcp_default_phase_possible()
1035 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1039 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
2109 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2158 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2162 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
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| A D | hsw_ips.c | 199 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
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| A D | icl_dsi.c | 1547 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1592 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1657 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1659 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
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| A D | intel_ddi.c | 402 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
416 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
494 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
496 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
3848 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3851 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3854 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3857 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3968 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
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| A D | intel_crt.c | 452 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
458 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
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| A D | intel_crtc_state_dump.c | 217 pipe_config->pipe_bpp, pipe_config->dither); in intel_crtc_state_dump()
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| A D | vlv_dsi.c | 296 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
298 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1047 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in bxt_dsi_get_pipe_config()
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| A D | intel_audio.c | 233 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
236 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
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| A D | intel_panel.c | 659 if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
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| A D | intel_display_debugfs.c | 577 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
1486 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); in i915_current_bpc_show()
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| A D | intel_modeset_setup.c | 321 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; in intel_modeset_update_connector_atomic_state()
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| A D | intel_vdsc.c | 307 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
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| A D | g4x_dp.c | 412 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_dp_get_config()
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| A D | intel_display_types.h | 1200 int pipe_bpp; /* in 1 bpp units */ member
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| A D | intel_psr.c | 1463 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1466 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
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| A D | intel_bios.c | 3552 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
3554 crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp, in fill_dsc()
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| A D | intel_tv.c | 1219 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
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