Searched refs:pipe_dlg_param (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | dml2_utils.c | 258 pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst; in populate_pipe_ctx_dlg_params_from_dml()
260 pipe_ctx->pipe_dlg_param.hactive = hactive; in populate_pipe_ctx_dlg_params_from_dml()
261 pipe_ctx->pipe_dlg_param.vactive = vactive; in populate_pipe_ctx_dlg_params_from_dml()
262 pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total; in populate_pipe_ctx_dlg_params_from_dml()
263 pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total; in populate_pipe_ctx_dlg_params_from_dml()
264 pipe_ctx->pipe_dlg_param.hblank_end = hblank_end; in populate_pipe_ctx_dlg_params_from_dml()
265 pipe_ctx->pipe_dlg_param.vblank_end = vblank_end; in populate_pipe_ctx_dlg_params_from_dml()
266 pipe_ctx->pipe_dlg_param.hblank_start = hblank_start; in populate_pipe_ctx_dlg_params_from_dml()
267 pipe_ctx->pipe_dlg_param.vblank_start = vblank_start; in populate_pipe_ctx_dlg_params_from_dml()
271 pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max; in populate_pipe_ctx_dlg_params_from_dml()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 1132 pipe_ctx->pipe_dlg_param.otg_inst = pipe_ctx->stream_res.tg->inst; in dml21_populate_pipe_ctx_dlg_params()
1134 pipe_ctx->pipe_dlg_param.hactive = hactive; in dml21_populate_pipe_ctx_dlg_params()
1135 pipe_ctx->pipe_dlg_param.vactive = vactive; in dml21_populate_pipe_ctx_dlg_params()
1136 pipe_ctx->pipe_dlg_param.htotal = pipe_ctx->stream->timing.h_total; in dml21_populate_pipe_ctx_dlg_params()
1137 pipe_ctx->pipe_dlg_param.vtotal = pipe_ctx->stream->timing.v_total; in dml21_populate_pipe_ctx_dlg_params()
1138 pipe_ctx->pipe_dlg_param.hblank_end = hblank_end; in dml21_populate_pipe_ctx_dlg_params()
1139 pipe_ctx->pipe_dlg_param.vblank_end = vblank_end; in dml21_populate_pipe_ctx_dlg_params()
1140 pipe_ctx->pipe_dlg_param.hblank_start = hblank_start; in dml21_populate_pipe_ctx_dlg_params()
1141 pipe_ctx->pipe_dlg_param.vblank_start = vblank_start; in dml21_populate_pipe_ctx_dlg_params()
1145 pipe_ctx->pipe_dlg_param.vtotal_max = pipe_ctx->stream->adjust.v_total_max; in dml21_populate_pipe_ctx_dlg_params()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| A D | dcn_calcs.c | 445 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; in pipe_ctx_to_e2e_pipe_params()
446 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
447 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; in pipe_ctx_to_e2e_pipe_params()
448 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; in pipe_ctx_to_e2e_pipe_params()
1212 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1214 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; in dcn_validate_bandwidth()
1215 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
1231 pipe->pipe_dlg_param.vblank_start = asic_blank_start; in dcn_validate_bandwidth()
1232 pipe->pipe_dlg_param.vblank_end = asic_blank_end; in dcn_validate_bandwidth()
1257 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; in dcn_validate_bandwidth()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| A D | dcn20_hwseq.c | 908 pipe_ctx->pipe_dlg_param.vready_offset, in dcn20_enable_stream_timing()
909 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_enable_stream_timing()
910 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn20_enable_stream_timing()
911 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn20_enable_stream_timing()
912 pipe_ctx->pipe_dlg_param.pstate_keepout, in dcn20_enable_stream_timing()
1548 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset in dcn20_detect_pipe_changes()
1549 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start in dcn20_detect_pipe_changes()
1550 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset in dcn20_detect_pipe_changes()
1551 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) in dcn20_detect_pipe_changes()
1685 &pipe_ctx->pipe_dlg_param); in dcn20_update_dchubp_dpp()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| A D | dcn10_hwseq.c | 938 int vready_offset = pipe->pipe_dlg_param.vready_offset; in calculate_vready_offset_for_group()
1005 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_enable_stream_timing()
1006 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn10_enable_stream_timing()
1007 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn10_enable_stream_timing()
1008 pipe_ctx->pipe_dlg_param.pstate_keepout, in dcn10_enable_stream_timing()
2845 &pipe_ctx->pipe_dlg_param); in dcn10_update_dchubp_dpp()
3002 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_program_pipe()
3003 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn10_program_pipe()
3004 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn10_program_pipe()
3005 pipe_ctx->pipe_dlg_param.pstate_keepout); in dcn10_program_pipe()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| A D | dcn401_hwseq.c | 867 pipe_ctx->pipe_dlg_param.vready_offset, in dcn401_enable_stream_timing()
868 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn401_enable_stream_timing()
869 pipe_ctx->pipe_dlg_param.vupdate_offset, in dcn401_enable_stream_timing()
870 pipe_ctx->pipe_dlg_param.vupdate_width, in dcn401_enable_stream_timing()
871 pipe_ctx->pipe_dlg_param.pstate_keepout, in dcn401_enable_stream_timing()
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 457 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; member
|
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_resource.c | 4444 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param) in adaptive_sync_override_dp_info_packets_sdp_line_num() argument
4459 if (pipe_dlg_param->vstartup_start > asic_blank_end) { in adaptive_sync_override_dp_info_packets_sdp_line_num()
4460 v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end)); in adaptive_sync_override_dp_info_packets_sdp_line_num()
4473 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param) in set_adaptive_sync_info_packet() argument
4481 pipe_dlg_param); in set_adaptive_sync_info_packet()
4548 &pipe_ctx->pipe_dlg_param); in resource_build_info_frame()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | dcn32_fpu.c | 357 pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn32_helper_populate_phantom_dlg_params()
1726 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn32_calculate_dlg_params()
1758 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); in dcn32_calculate_dlg_params()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | dcn20_fpu.c | 1203 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; in dcn20_calculate_dlg_params()
1208 &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); in dcn20_calculate_dlg_params()
|
| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_dmub_srv.c | 672 pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; in populate_subvp_cmd_vblank_pipe_info()
|
Completed in 54 milliseconds