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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddcn20_fpu.c1238 pipes, in dcn20_calculate_dlg_params()
1247 &pipes[pipe_idx].pipe); in dcn20_calculate_dlg_params()
1390 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start in dcn20_populate_dml_pipes_from_context()
1395 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start in dcn20_populate_dml_pipes_from_context()
1560 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height; in dcn20_populate_dml_pipes_from_context()
1561 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width; in dcn20_populate_dml_pipes_from_context()
1562 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height; in dcn20_populate_dml_pipes_from_context()
1563 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width; in dcn20_populate_dml_pipes_from_context()
1797 pipes[0].clks_cfg.voltage = 1; in dcn20_calculate_wm()
1811 pipes[0].clks_cfg.voltage = 2; in dcn20_calculate_wm()
[all …]
A Ddcn20_fpu.h33 display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
41 display_e2e_pipe_params_st *pipes,
46 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
65 bool fast_validate, display_e2e_pipe_params_st *pipes);
77 display_e2e_pipe_params_st *pipes,
80 fast_validate, display_e2e_pipe_params_st *pipes);
87 display_e2e_pipe_params_st *pipes);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c296 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel() argument
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
414 display_e2e_pipe_params_st *pipes, in dcn301_fpu_calculate_wm_and_dlg() argument
435 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
440 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
445 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
451 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
457 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_fpu_calculate_wm_and_dlg()
458 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_fpu_calculate_wm_and_dlg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddcn30_fpu.c275 pipes[pipe_cnt].dout.wb_enable = 0; in dcn30_fpu_populate_dml_writeback_from_context()
282 pipes[pipe_cnt].dout.wb_enable = 1; in dcn30_fpu_populate_dml_writeback_from_context()
333 pipes[pipe_cnt].pipe.dest.htotal, in dcn30_fpu_populate_dml_writeback_from_context()
338 pipes[pipe_cnt].dout.wb = dout_wb; in dcn30_fpu_populate_dml_writeback_from_context()
349 display_e2e_pipe_params_st *pipes, in dcn30_fpu_set_mcif_arb_params() argument
381 display_e2e_pipe_params_st *pipes, in dcn30_fpu_calculate_wm_and_dlg() argument
410 context, pipes, pipe_cnt, vlevel); in dcn30_fpu_calculate_wm_and_dlg()
428 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
438 pipes[0].clks_cfg.voltage = 1; in dcn30_fpu_calculate_wm_and_dlg()
454 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
[all …]
A Ddcn30_fpu.h36 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
40 display_e2e_pipe_params_st *pipes,
48 display_e2e_pipe_params_st *pipes,
68 display_e2e_pipe_params_st *pipes,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
A Ddcn314_fpu.c308 display_e2e_pipe_params_st *pipes, in dcn314_populate_dml_pipes_from_context_fpu() argument
340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn314_populate_dml_pipes_from_context_fpu()
341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn314_populate_dml_pipes_from_context_fpu()
346 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn314_populate_dml_pipes_from_context_fpu()
348 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn314_populate_dml_pipes_from_context_fpu()
370 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn314_populate_dml_pipes_from_context_fpu()
371 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn314_populate_dml_pipes_from_context_fpu()
373 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn314_populate_dml_pipes_from_context_fpu()
376 pipes[pipe_cnt].dout.dsc_input_bpc = 8; in dcn314_populate_dml_pipes_from_context_fpu()
379 pipes[pipe_cnt].dout.dsc_input_bpc = 10; in dcn314_populate_dml_pipes_from_context_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/
A Ddcn35_fpu.c466 pipes[pipe_cnt].pipe.dest.vtotal = in dcn35_populate_dml_pipes_from_context_fpu()
469 pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
472 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
473 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn35_populate_dml_pipes_from_context_fpu()
478 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn35_populate_dml_pipes_from_context_fpu()
480 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn35_populate_dml_pipes_from_context_fpu()
504 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn35_populate_dml_pipes_from_context_fpu()
505 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn35_populate_dml_pipes_from_context_fpu()
508 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn35_populate_dml_pipes_from_context_fpu()
511 pipes[pipe_cnt].dout.dsc_input_bpc = 8; in dcn35_populate_dml_pipes_from_context_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/
A Ddcn351_fpu.c500 pipes[pipe_cnt].pipe.dest.vtotal = in dcn351_populate_dml_pipes_from_context_fpu()
503 pipes[pipe_cnt].pipe.dest.vactive; in dcn351_populate_dml_pipes_from_context_fpu()
506 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn351_populate_dml_pipes_from_context_fpu()
507 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn351_populate_dml_pipes_from_context_fpu()
512 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn351_populate_dml_pipes_from_context_fpu()
514 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn351_populate_dml_pipes_from_context_fpu()
538 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn351_populate_dml_pipes_from_context_fpu()
539 pipes[pipe_cnt].dout.dsc_input_bpc = 0; in dcn351_populate_dml_pipes_from_context_fpu()
542 if (pipes[pipe_cnt].dout.dsc_enable) { in dcn351_populate_dml_pipes_from_context_fpu()
545 pipes[pipe_cnt].dout.dsc_input_bpc = 8; in dcn351_populate_dml_pipes_from_context_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
A Ddcn32_fpu.h36 display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
49 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes,
63 display_e2e_pipe_params_st *pipes,
69 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
A Ddcn32_fpu.c506 pipes[0].clks_cfg.voltage = vlevel; in dcn32_set_phantom_stream_timing()
1394 display_e2e_pipe_params_st *pipes, in try_odm_power_optimization_and_revalidate() argument
1521 pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0); in dcn32_full_validate_bw_helper()
1701 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, in dcn32_calculate_dlg_params()
1703 …pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cn… in dcn32_calculate_dlg_params()
1705 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, in dcn32_calculate_dlg_params()
1707 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, in dcn32_calculate_dlg_params()
2151 ASSERT(pipes); in dcn32_internal_validate_bw()
2152 if (!pipes) in dcn32_internal_validate_bw()
2494 pipes[0].clks_cfg.voltage = vlevel; in dcn32_calculate_wm_and_dlg_fpu()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
A Ddcn30_resource.h51 display_e2e_pipe_params_st *pipes,
64 display_e2e_pipe_params_st *pipes,
71 display_e2e_pipe_params_st *pipes,
76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
80 display_e2e_pipe_params_st *pipes,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddcn31_fpu.c445 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, in dcn31_zero_pipe_dcc_fraction() argument
450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_zero_pipe_dcc_fraction()
451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_zero_pipe_dcc_fraction()
484 display_e2e_pipe_params_st *pipes, in dcn31_calculate_wm_and_dlg_fp() argument
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
511 get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
544 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
545 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
554 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
[all …]
A Ddcn31_fpu.h35 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
57 display_e2e_pipe_params_st *pipes,
/linux/sound/sparc/
A Ddbri.c769 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; in dbri_initialize()
833 sdp = dbri->pipes[pipe].sdp; in reset_pipe()
854 dbri->pipes[pipe].desc = -1; in reset_pipe()
882 dbri->pipes[pipe].sdp = sdp; in setup_pipe()
883 dbri->pipes[pipe].desc = -1; in setup_pipe()
907 if (dbri->pipes[pipe].sdp == 0 in link_time_slot()
1258 dbri->pipes[16].sdp = 1; in reset_chi()
1259 dbri->pipes[16].nextpipe = 16; in reset_chi()
1783 int td = dbri->pipes[pipe].desc; in transmission_complete_intr()
1802 dbri->pipes[pipe].desc = td; in transmission_complete_intr()
[all …]
/linux/drivers/platform/goldfish/
A Dgoldfish_pipe.c522 pipe = dev->pipes[id]; in signalled_pipes_add_locked()
654 if (!dev->pipes[id]) in get_free_pipe_id_locked()
665 if (!pipes) in get_free_pipe_id_locked()
667 memcpy(pipes, dev->pipes, sizeof(*pipes) * dev->pipes_capacity); in get_free_pipe_id_locked()
668 kfree(dev->pipes); in get_free_pipe_id_locked()
669 dev->pipes = pipes; in get_free_pipe_id_locked()
732 dev->pipes[id] = pipe; in goldfish_pipe_open()
830 dev->pipes = kcalloc(dev->pipes_capacity, sizeof(*dev->pipes), in goldfish_pipe_device_init()
832 if (!dev->pipes) { in goldfish_pipe_device_init()
847 kfree(dev->pipes); in goldfish_pipe_device_init()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.c46 const display_e2e_pipe_params_st *pipes,
54 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level() argument
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
209 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes() argument
218 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bw() argument
231 const display_e2e_pipe_params_st *pipes, in get_total_prefetch_bw() argument
245 const display_e2e_pipe_params_st *pipes, in get_total_surface_size_in_mall_bytes() argument
882 …mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable || !!pipes[k].pipe.src.gpuvm || !!pipes[k].p… in fetch_pipe_params()
967 pipes, in recalculate_params()
[all …]
A Ddisplay_mode_lib.c162 display_e2e_pipe_params_st *pipes, in dml_log_pipe_params() argument
174 pipe_src = &(pipes[i].pipe.src); in dml_log_pipe_params()
175 pipe_dest = &(pipes[i].pipe.dest); in dml_log_pipe_params()
176 scale_ratio_depth = &(pipes[i].pipe.scale_ratio_depth); in dml_log_pipe_params()
177 scale_taps = &(pipes[i].pipe.scale_taps); in dml_log_pipe_params()
178 dout = &(pipes[i].dout); in dml_log_pipe_params()
179 clks_cfg = &(pipes[i].clks_cfg); in dml_log_pipe_params()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
A Ddcn31_resource.h45 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes);
59 display_e2e_pipe_params_st *pipes,
/linux/drivers/gpu/drm/arm/display/komeda/
A Dkomeda_event.c110 return (a->pipes[0] | a->pipes[1]) & in is_new_frame()
120 u64 evts_mask = evts->global | evts->pipes[0] | evts->pipes[1]; in komeda_print_events()
147 evt_str(&str, evts->pipes[0]); in komeda_print_events()
149 evt_str(&str, evts->pipes[1]); in komeda_print_events()
/linux/drivers/gpu/drm/tidss/
A Dtidss_kms.c120 struct pipe pipes[TIDSS_MAX_PORTS]; in tidss_dispc_modeset_init() local
177 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
178 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
179 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
204 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, in tidss_dispc_modeset_init()
213 ret = tidss_encoder_create(tidss, pipes[i].bridge, in tidss_dispc_modeset_init()
214 pipes[i].enc_type, in tidss_dispc_modeset_init()
/linux/Documentation/gpu/amdgpu/display/
A Dmpo-overview.rst50 For this hardware example, we have 4 pipes (if you don't know what AMD pipe
53 configuration for optimal single display output (e.g., 2 pipes per plane).
56 display - will see 4 pipes in use, 2 per plane.
207 - 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
208 - 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
209 middle of both displays needs 2 pipes.
210 - 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
221 on an ASIC that only supports three pipes. We can have:
225 - Total pipes are 3
226 - User lights up 2 displays (2 out of 3 pipes are used)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml2/
A Ddml2_dc_resource_mgmt.c142 struct dc_state *state, unsigned int plane_id, unsigned int *pipes) in find_pipes_assigned_to_plane() argument
163 pipes[num_found++] = mpc_pipe->pipe_idx; in find_pipes_assigned_to_plane()
451 static void sort_pipes_for_splitting(struct dc_plane_pipe_pool *pipes) in sort_pipes_for_splitting() argument
462 if (pipes->num_pipes_assigned_to_plane_for_mpcc_combine <= 1) in sort_pipes_for_splitting()
470 …if (pipes->pipes_assigned_to_plane[odm_slice_index][cur_index] > pipes->pipes_assigned_to_plane[od… in sort_pipes_for_splitting()
471 temp = pipes->pipes_assigned_to_plane[odm_slice_index][cur_index]; in sort_pipes_for_splitting()
472 …pipes->pipes_assigned_to_plane[odm_slice_index][cur_index] = pipes->pipes_assigned_to_plane[odm_sl… in sort_pipes_for_splitting()
473 pipes->pipes_assigned_to_plane[odm_slice_index][cur_index + 1] = temp; in sort_pipes_for_splitting()
594 pipes[num_found++] = pipe->pipe_idx; in find_pipes_assigned_to_stream()
613 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_stream() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
A Ddcn32_resource_helpers.c313 display_e2e_pipe_params_st *pipes) in dcn32_determine_det_override() argument
382 display_e2e_pipe_params_st *pipes) in dcn32_set_det_allocations() argument
403 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE; in dcn32_set_det_allocations()
406 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE; in dcn32_set_det_allocations()
407 pipes[0].pipe.src.unbounded_req_mode = true; in dcn32_set_det_allocations()
410 pipes[0].pipe.src.det_size_override = 320; // 5K or higher in dcn32_set_det_allocations()
414 dcn32_determine_det_override(dc, context, pipes); in dcn32_set_det_allocations()
751 display_e2e_pipe_params_st *pipes) in dcn32_update_dml_pipes_odm_policy_based_on_context() argument
766 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; in dcn32_update_dml_pipes_odm_policy_based_on_context()
768 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; in dcn32_update_dml_pipes_odm_policy_based_on_context()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
A Dlink_dp_cts.c68 struct pipe_ctx *pipes[MAX_PIPES]; in dp_retrain_link_dp_test() local
77 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); in dp_retrain_link_dp_test()
80 link_set_dpms_off(pipes[i]); in dp_retrain_link_dp_test()
81 pipes[i]->link_config.dp_link_settings = *link_setting; in dp_retrain_link_dp_test()
85 pipes[i]); in dp_retrain_link_dp_test()
95 link_set_dpms_on(state, pipes[i]); in dp_retrain_link_dp_test()
135 struct pipe_ctx *pipe_ctx = &pipes[0]; in dp_test_get_audio_test_data()
605 if (pipes[i].stream == NULL) in dp_set_test_pattern()
608 if (resource_is_pipe_type(&pipes[i], OTG_MASTER) && in dp_set_test_pattern()
609 pipes[i].stream->link == link) { in dp_set_test_pattern()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_dp_irq_handler.c270 struct pipe_ctx *pipes[MAX_PIPES]; in dp_handle_link_loss() local
275 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); in dp_handle_link_loss()
278 link_set_dpms_off(pipes[i]); in dp_handle_link_loss()
283 pipes[i]->link_config.dp_link_settings.lane_count = in dp_handle_link_loss()
285 pipes[i]->link_config.dp_link_settings.link_rate = in dp_handle_link_loss()
287 pipes[i]->link_config.dp_link_settings.link_spread = in dp_handle_link_loss()
290 link_set_dpms_on(link->dc->current_state, pipes[i]); in dp_handle_link_loss()

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