| /linux/Documentation/devicetree/bindings/clock/ |
| A D | fsl,qoriq-clock.yaml | 166 pll0: pll0@800 {
171 clock-output-names = "pll0", "pll0-div2";
186 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
187 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
195 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
196 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| A D | renesas,cpg-clocks.yaml | 78 - const: pll0
204 - const: pll0
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| A D | imx28-clock.yaml | 20 pll0 1
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| A D | renesas,cpg-div6-clock.yaml | 60 clock-output-names = "main", "pll0", "pll1", "pll2",
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| /linux/drivers/bcma/ |
| A D | driver_chipcommon_pmu.c | 84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); in bcma_pmu_pll_clock()
370 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); in bcma_pmu_pll_clock()
374 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); in bcma_pmu_pll_clock()
[all …]
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| /linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
| A D | pll.txt | 9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
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| /linux/Documentation/devicetree/bindings/clock/st/ |
| A D | st,clkgen-pll.txt | 12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
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| A D | st,clkgen.txt | 51 compatible = "st,clkgen-pll0";
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| /linux/arch/arc/boot/dts/ |
| A D | abilis_tb10x.dtsi | 48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
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| A D | abilis_tb100.dtsi | 17 pll0: oscillator { label
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| A D | abilis_tb101.dtsi | 17 pll0: oscillator { label
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| /linux/arch/arm/boot/dts/st/ |
| A D | stih410-clock.dtsi | 75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
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| A D | stih418-clock.dtsi | 75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
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| A D | stih407-clock.dtsi | 70 compatible = "st,clkgen-pll0-a0";
89 clk_s_c0_pll0: clk-s-c0-pll0 {
91 compatible = "st,clkgen-pll0-c0";
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| /linux/drivers/gpu/drm/tegra/ |
| A D | hdmi.c | 44 u32 pll0; member
140 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
155 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
173 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
187 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
201 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
219 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
237 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
256 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
275 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
[all …]
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| A D | sor.c | 367 unsigned int pll0; member
1459 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
2295 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2493 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
3284 .pll0 = 0x17,
3456 .pll0 = 0x17,
3517 .pll0 = 0x163,
[all …]
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| /linux/Documentation/devicetree/bindings/display/ |
| A D | intel,keembay-display.yaml | 28 - description: pll0 clock
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| /linux/drivers/clk/mxs/ |
| A D | clk-imx28.c | 133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
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| /linux/arch/arm/boot/dts/marvell/ |
| A D | dove-cubox.dts | 101 /* connect xtal input as source of pll0 and pll1 */
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| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_dpll_mgr.h | 209 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| A D | intel_dpll_mgr.c | 2069 PORT_PLL_M2_INT_MASK, hw_state->pll0); in bxt_ddi_pll_enable()
2187 hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2188 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()
2331 hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22); in bxt_ddi_set_dpll_hw_state()
2364 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, hw_state->pll0) << 22; in bxt_ddi_pll_get_freq()
2460 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2473 a->pll0 == b->pll0 && in bxt_compare_hw_state()
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| /linux/drivers/phy/ti/ |
| A D | Kconfig | 49 three clock selects (pll0, pll1, dig) and resets for each of the
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| /linux/drivers/clk/qcom/ |
| A D | gcc-mdm9615.c | 47 static struct clk_pll pll0 = { variable
69 &pll0.clkr.hw,
1615 [PLL0] = &pll0.clkr,
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| /linux/Documentation/devicetree/bindings/phy/ |
| A D | ti,phy-j721e-wiz.yaml | 216 pll0-refclk {
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| /linux/arch/arm/boot/dts/ti/davinci/ |
| A D | da850.dtsi | 135 pll0: clock-controller@11000 { label
136 compatible = "ti,da850-pll0";
|