Searched refs:pll3 (Results 1 – 15 of 15) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ |
| A D | allwinner,sun4i-a10-pll3-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
20 const: allwinner,sun4i-a10-pll3-clk
44 compatible = "allwinner,sun4i-a10-pll3-clk";
47 clock-output-names = "pll3";
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| A D | allwinner,sun4i-a10-tcon-ch0-clk.yaml | 64 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
73 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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| A D | allwinner,sun9i-a80-cpus-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
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| A D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
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| A D | renesas,cpg-clocks.yaml | 207 - const: pll3
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| A D | qcom,mmcc.yaml | 94 - const: pll3
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| /linux/drivers/clk/sunxi/ |
| A D | Makefile | 18 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sun4i-pll3.o
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| /linux/drivers/gpu/drm/i915/display/ |
| A D | intel_dpll_mgr.h | 209 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| A D | intel_dpll_mgr.c | 2081 PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3); in bxt_ddi_pll_enable()
2196 hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); in bxt_ddi_pll_get_hw_state()
2197 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_pll_get_hw_state()
2336 hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE; in bxt_ddi_set_dpll_hw_state()
2365 if (hw_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) in bxt_ddi_pll_get_freq()
2460 hw_state->pll0, hw_state->pll1, hw_state->pll2, hw_state->pll3, in bxt_dump_hw_state()
2476 a->pll3 == b->pll3 && in bxt_compare_hw_state()
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| /linux/drivers/gpu/drm/tegra/ |
| A D | sor.c | 370 unsigned int pll3; member
2291 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2511 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2774 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
3287 .pll3 = 0x1a,
3459 .pll3 = 0x1a,
3520 .pll3 = 0x166,
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| /linux/drivers/clk/qcom/ |
| A D | gcc-ipq806x.c | 61 static struct clk_pll pll3 = { variable
324 { .hw = &pll3.clkr.hw },
385 { .hw = &pll3.clkr.hw },
3069 [PLL3] = &pll3.clkr,
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| A D | gcc-msm8960.c | 29 static struct clk_pll pll3 = { variable
328 { .hw = &pll3.clkr.hw },
3243 [PLL3] = &pll3.clkr,
3471 [PLL3] = &pll3.clkr,
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| /linux/arch/arm/boot/dts/qcom/ |
| A D | qcom-msm8960.dtsi | 176 "pll3",
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| A D | qcom-apq8064.dtsi | 742 "pll3",
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| /linux/arch/arm/boot/dts/renesas/ |
| A D | sh73a0.dtsi | 652 "pll3", "dsi0phy", "dsi1phy",
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