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Searched refs:post_div_table (Results 1 – 25 of 52) sorted by relevance

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/linux/drivers/clk/qcom/
A Dcamcc-sc7280.c86 .post_div_table = post_div_table_cam_cc_pll0_out_even,
109 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
161 .post_div_table = post_div_table_cam_cc_pll1_out_even,
211 .post_div_table = post_div_table_cam_cc_pll2_out_aux,
234 .post_div_table = post_div_table_cam_cc_pll2_out_aux2,
286 .post_div_table = post_div_table_cam_cc_pll3_out_even,
338 .post_div_table = post_div_table_cam_cc_pll4_out_even,
390 .post_div_table = post_div_table_cam_cc_pll5_out_even,
442 .post_div_table = post_div_table_cam_cc_pll6_out_even,
465 .post_div_table = post_div_table_cam_cc_pll6_out_odd,
A Dcamcc-sm8550.c100 .post_div_table = post_div_table_cam_cc_pll0_out_even,
123 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
177 .post_div_table = post_div_table_cam_cc_pll1_out_even,
258 .post_div_table = post_div_table_cam_cc_pll3_out_even,
312 .post_div_table = post_div_table_cam_cc_pll4_out_even,
366 .post_div_table = post_div_table_cam_cc_pll5_out_even,
420 .post_div_table = post_div_table_cam_cc_pll6_out_even,
474 .post_div_table = post_div_table_cam_cc_pll7_out_even,
528 .post_div_table = post_div_table_cam_cc_pll8_out_even,
582 .post_div_table = post_div_table_cam_cc_pll9_out_even,
[all …]
A Dclk-alpha-pll.c1498 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1499 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1520 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1521 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1549 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1550 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1595 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1596 val = pll->post_div_table[i].val; in clk_alpha_pll_postdiv_fabia_set_rate()
2016 if (!pll->post_div_table) { in __clk_lucid_pll_postdiv_set_rate()
2024 if (pll->post_div_table[i].div == div) { in __clk_lucid_pll_postdiv_set_rate()
[all …]
A Dcamcc-sm4450.c86 .post_div_table = post_div_table_cam_cc_pll0_out_even,
109 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
160 .post_div_table = post_div_table_cam_cc_pll1_out_even,
211 .post_div_table = post_div_table_cam_cc_pll2_out_even,
262 .post_div_table = post_div_table_cam_cc_pll3_out_even,
313 .post_div_table = post_div_table_cam_cc_pll4_out_even,
A Dcamcc-sm8650.c98 .post_div_table = post_div_table_cam_cc_pll0_out_even,
121 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
175 .post_div_table = post_div_table_cam_cc_pll1_out_even,
256 .post_div_table = post_div_table_cam_cc_pll3_out_even,
310 .post_div_table = post_div_table_cam_cc_pll4_out_even,
364 .post_div_table = post_div_table_cam_cc_pll5_out_even,
418 .post_div_table = post_div_table_cam_cc_pll6_out_even,
472 .post_div_table = post_div_table_cam_cc_pll7_out_even,
526 .post_div_table = post_div_table_cam_cc_pll8_out_even,
580 .post_div_table = post_div_table_cam_cc_pll9_out_even,
[all …]
A Dgpucc-sm6115.c90 .post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
145 .post_div_table = post_div_table_gpu_cc_pll1_out_aux,
A Dlpassaudiocc-sc7280.c105 .post_div_table = post_div_table_lpass_audio_cc_pll_out_aux2,
160 .post_div_table = post_div_table_lpass_aon_cc_pll_out_even,
182 .post_div_table = post_div_table_lpass_aon_cc_pll_out_odd,
A Dcamcc-sm8450.c92 .post_div_table = post_div_table_cam_cc_pll0_out_even,
115 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
163 .post_div_table = post_div_table_cam_cc_pll1_out_even,
234 .post_div_table = post_div_table_cam_cc_pll3_out_even,
282 .post_div_table = post_div_table_cam_cc_pll4_out_even,
330 .post_div_table = post_div_table_cam_cc_pll5_out_even,
378 .post_div_table = post_div_table_cam_cc_pll6_out_even,
426 .post_div_table = post_div_table_cam_cc_pll7_out_even,
474 .post_div_table = post_div_table_cam_cc_pll8_out_even,
A Dcamcc-sc8280xp.c94 .post_div_table = post_div_table_camcc_pll0_out_even,
116 .post_div_table = post_div_table_camcc_pll0_out_odd,
169 .post_div_table = post_div_table_camcc_pll1_out_even,
247 .post_div_table = post_div_table_camcc_pll3_out_even,
300 .post_div_table = post_div_table_camcc_pll4_out_even,
353 .post_div_table = post_div_table_camcc_pll5_out_even,
406 .post_div_table = post_div_table_camcc_pll6_out_even,
459 .post_div_table = post_div_table_camcc_pll7_out_even,
481 .post_div_table = post_div_table_camcc_pll7_out_odd,
A Dcamcc-sm8150.c89 .post_div_table = post_div_table_cam_cc_pll0_out_even,
112 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
166 .post_div_table = post_div_table_cam_cc_pll1_out_even,
220 .post_div_table = post_div_table_cam_cc_pll2_out_main,
274 .post_div_table = post_div_table_cam_cc_pll3_out_even,
328 .post_div_table = post_div_table_cam_cc_pll4_out_even,
A Dcamcc-x1e80100.c93 .post_div_table = post_div_table_cam_cc_pll0_out_even,
116 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
170 .post_div_table = post_div_table_cam_cc_pll1_out_even,
251 .post_div_table = post_div_table_cam_cc_pll3_out_even,
305 .post_div_table = post_div_table_cam_cc_pll4_out_even,
359 .post_div_table = post_div_table_cam_cc_pll6_out_even,
413 .post_div_table = post_div_table_cam_cc_pll8_out_even,
A Dclk-alpha-pll.h118 const struct clk_div_table *post_div_table; member
A Dgcc-sm6115.c84 .post_div_table = post_div_table_gpll0_out_aux2,
104 .post_div_table = post_div_table_gpll0_out_main,
154 .post_div_table = post_div_table_gpll10_out_main,
208 .post_div_table = post_div_table_gpll11_out_main,
267 .post_div_table = post_div_table_gpll4_out_main,
306 .post_div_table = post_div_table_gpll6_out_main,
345 .post_div_table = post_div_table_gpll7_out_main,
402 .post_div_table = post_div_table_gpll8_out_main,
454 .post_div_table = post_div_table_gpll9_out_main,
A Dmmcc-msm8998.c76 .post_div_table = post_div_table_fabia_even,
108 .post_div_table = post_div_table_fabia_even,
136 .post_div_table = post_div_table_fabia_even,
164 .post_div_table = post_div_table_fabia_even,
192 .post_div_table = post_div_table_fabia_even,
220 .post_div_table = post_div_table_fabia_even,
248 .post_div_table = post_div_table_fabia_even,
276 .post_div_table = post_div_table_fabia_even,
A Dcamcc-sm8250.c79 .post_div_table = post_div_table_cam_cc_pll0_out_even,
102 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
153 .post_div_table = post_div_table_cam_cc_pll1_out_even,
204 .post_div_table = post_div_table_cam_cc_pll2_out_main,
255 .post_div_table = post_div_table_cam_cc_pll3_out_even,
306 .post_div_table = post_div_table_cam_cc_pll4_out_even,
A Dcamcc-sdm845.c52 .post_div_table = post_div_table_fabia_even,
84 .post_div_table = post_div_table_fabia_even,
116 .post_div_table = post_div_table_fabia_even,
148 .post_div_table = post_div_table_fabia_even,
A Dgpucc-msm8998.c80 .post_div_table = post_div_table_fabia_even,
A Dlpasscorecc-sc7280.c73 .post_div_table = post_div_table_lpass_core_cc_dig_pll_out_odd,
A Dlpasscorecc-sc7180.c89 .post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
/linux/drivers/clk/imx/
A Dclk-imx6sl.c80 static const struct clk_div_table post_div_table[] = { variable
267 …v", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
269 …v", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
A Dclk-imx6sll.c59 static const struct clk_div_table post_div_table[] = { variable
176 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
180 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
A Dclk-imx6q.c104 static struct clk_div_table post_div_table[] = { variable
467 post_div_table[1].div = 1; in imx6q_clocks_init()
468 post_div_table[2].div = 1; in imx6q_clocks_init()
598 …post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
603 …post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
A Dclk-imx6ul.c83 static const struct clk_div_table post_div_table[] = { variable
233 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
237 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
A Dclk-imx6sx.c96 static const struct clk_div_table post_div_table[] = { variable
249 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
253 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
A Dclk-imx7d.c36 static const struct clk_div_table post_div_table[] = { variable
434 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
438 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()

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