| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dm_pp_smu.h | 49 struct pp_smu { struct
98 struct pp_smu pp_smu; member
104 void (*set_display_count)(struct pp_smu *pp, int count);
113 void (*set_wm_ranges)(struct pp_smu *pp,
138 void (*set_pme_wa_enable)(struct pp_smu *pp);
169 struct pp_smu pp_smu; member
218 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
272 struct pp_smu pp_smu; member
282 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
290 struct pp_smu pp_smu; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| A D | rv1_clk_mgr.c | 207 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
221 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in rv1_update_clocks()
264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
266 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
284 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
285 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
286 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_k… in rv1_update_clocks()
297 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_enable_pme_wa()
300 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); in rv1_enable_pme_wa()
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| A D | rv2_clk_mgr.c | 37 …gr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
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| A D | rv1_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
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| A D | rv2_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
254 if (pp_smu && pp_smu->set_display_count) in dcn2_update_clocks()
255 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in dcn2_update_clocks()
264 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
271 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
292 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) in dcn2_update_clocks()
317 if (pp_smu && pp_smu->set_voltage_by_freq) in dcn2_update_clocks()
417 pp_smu = &clk_mgr->pp_smu->nv_funcs; in dcn2_enable_pme_wa()
420 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); in dcn2_enable_pme_wa()
502 pp_smu = &clk_mgr->pp_smu->nv_funcs; in dcn2_notify_link_rate_change()
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| A D | dcn20_clk_mgr.h | 43 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| A D | clk_mgr.c | 233 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
238 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
242 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
247 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
260 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
264 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
268 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
275 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
286 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
299 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_pp_smu.c | 464 static void pp_rv_set_wm_ranges(struct pp_smu *pp, in pp_rv_set_wm_ranges()
513 static void pp_rv_set_pme_wa_enable(struct pp_smu *pp) in pp_rv_set_pme_wa_enable()
581 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) in pp_nv_set_min_deep_sleep_dcfclk()
598 struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_dcefclk_by_freq()
621 pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_uclk_by_freq()
644 struct pp_smu *pp, bool pstate_handshake_supported) in pp_nv_set_pstate_handshake_support()
692 struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks) in pp_nv_get_maximum_sustainable_clocks()
727 struct pp_smu *pp, struct dpm_clocks *clock_table) in pp_rn_get_dpm_clock_table()
761 funcs->rv_funcs.pp_smu.dm = ctx; in dm_pp_get_funcs()
775 funcs->nv_funcs.pp_smu.dm = ctx; in dm_pp_get_funcs()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr.c | 516 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; in rn_notify_wm_ranges() local
522 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) in rn_notify_wm_ranges()
523 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
703 struct pp_smu_funcs *pp_smu, in rn_clk_mgr_construct() argument
717 clk_mgr->pp_smu = pp_smu; in rn_clk_mgr_construct()
771 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { in rn_clk_mgr_construct()
772 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); in rn_clk_mgr_construct()
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| A D | rn_clk_mgr.h | 46 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| A D | dcn20_resource.c | 2316 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); in dcn20_pp_smu_create() local
2318 if (!pp_smu) in dcn20_pp_smu_create()
2319 return pp_smu; in dcn20_pp_smu_create()
2324 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn20_pp_smu_create()
2326 return pp_smu; in dcn20_pp_smu_create()
2331 if (pp_smu && *pp_smu) { in dcn20_pp_smu_destroy()
2332 kfree(*pp_smu); in dcn20_pp_smu_destroy()
2333 *pp_smu = NULL; in dcn20_pp_smu_destroy()
2384 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2391 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); in init_soc_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| A D | dcn21_resource.c | 763 if (pool->base.pp_smu != NULL) in dcn21_resource_destruct()
1107 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn21_pp_smu_create() local
1109 if (!pp_smu) in dcn21_pp_smu_create()
1110 return pp_smu; in dcn21_pp_smu_create()
1112 dm_pp_get_funcs(ctx, pp_smu); in dcn21_pp_smu_create()
1114 if (pp_smu->ctx.ver != PP_SMU_VER_RN) in dcn21_pp_smu_create()
1115 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn21_pp_smu_create()
1118 return pp_smu; in dcn21_pp_smu_create()
1123 if (pp_smu && *pp_smu) { in dcn21_pp_smu_destroy()
1124 kfree(*pp_smu); in dcn21_pp_smu_destroy()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| A D | dcn201_clk_mgr.h | 31 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| A D | dcn32_clk_mgr.h | 32 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| A D | dcn315_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| A D | dcn316_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
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| A D | dcn316_clk_mgr.c | 576 struct pp_smu_funcs *pp_smu, in dcn316_clk_mgr_construct() argument
585 clk_mgr->base.pp_smu = pp_smu; in dcn316_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| A D | dcn10_resource.c | 903 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn10_pp_smu_create() local
905 if (!pp_smu) in dcn10_pp_smu_create()
906 return pp_smu; in dcn10_pp_smu_create()
908 dm_pp_get_funcs(ctx, pp_smu); in dcn10_pp_smu_create()
909 return pp_smu; in dcn10_pp_smu_create()
988 kfree(pool->base.pp_smu); in dcn10_resource_destruct()
1495 pool->base.pp_smu = dcn10_pp_smu_create(ctx); in dcn10_resource_construct()
1501 if (pool->base.pp_smu != NULL in dcn10_resource_construct()
1502 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | vg_clk_mgr.h | 47 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.h | 51 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| A D | dcn35_clk_mgr.h | 58 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| A D | dcn314_clk_mgr.h | 63 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.h | 93 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 1324 struct pp_smu_funcs *pp_smu, in set_wm_ranges() argument
1364 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); in set_wm_ranges()
1557 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) in dcn301_resource_construct()
1558 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); in dcn301_resource_construct()
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