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Searched refs:reference_divider (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/radeon/
A Drv730_dpm.c50 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local
59 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
94 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_sclk_value()
129 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local
137 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()
170 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_mclk_value()
A Drv740_dpm.c131 u32 reference_divider; in rv740_populate_sclk_value() local
140 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
163 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv740_populate_sclk_value()
A Drv770_dpm.c326 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local
335 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
338 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()
503 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local
512 reference_divider = 1 + dividers.ref_div; in rv770_populate_sclk_value()
519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
545 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv770_populate_sclk_value()
A Dni_dpm.c2013 u32 reference_divider; in ni_calculate_sclk_params() local
2022 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()
2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2046 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ni_calculate_sclk_params()
A Dsi_dpm.c4734 u32 reference_divider; in si_calculate_sclk_params() local
4743 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()
4745 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
4766 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()
A Dci_dpm.c3126 u32 reference_divider; in ci_calculate_sclk_params() local
3136 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()
3149 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params()
/linux/drivers/gpu/drm/amd/display/include/
A Dbios_parser_types.h209 uint32_t reference_divider; member
226 uint32_t reference_divider; member
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clock_source.c238 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()
338 if (pll_settings->reference_divider) { in calculate_pixel_clock_pll_dividers()
339 min_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()
340 max_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()
453 pll_settings->reference_divider = in pll_adjust_pix_clk()
454 bp_adjust_pixel_clock_params.reference_divider; in pll_adjust_pix_clk()
699 pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz); in calculate_ss()
869 bp_pc_params.reference_divider = pll_settings->reference_divider; in dce110_program_pix_clk()
/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dclock_source.h113 uint32_t reference_divider; member
/linux/drivers/gpu/drm/amd/display/dc/bios/
A Dcommand_table.c992 cpu_to_le16((uint16_t)bp_params->reference_divider); in set_pixel_clock_v3()
1063 (uint8_t)(bp_params->reference_divider); in set_pixel_clock_v5()
1152 (uint8_t) bp_params->reference_divider; in set_pixel_clock_v6()
1603 bp_params->reference_divider = params.sOutput.ucRefDiv; in adjust_display_pll_v3()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Diceland_smumgr.c806 uint32_t reference_divider; in iceland_calculate_sclk_params() local
819 reference_divider = 1 + dividers.uc_pll_ref_div; in iceland_calculate_sclk_params()
849 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in iceland_calculate_sclk_params()
A Dtonga_smumgr.c549 uint32_t reference_divider; in tonga_calculate_sclk_params() local
562 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()
592 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in tonga_calculate_sclk_params()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dsi_dpm.c5280 u32 reference_divider; in si_calculate_sclk_params() local
5289 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()
5291 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
5312 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()

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