Home
last modified time | relevance | path

Searched refs:reg_layout (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/soundwire/
A Dqcom.c182 const unsigned int *reg_layout; member
221 const unsigned int *reg_layout; member
240 .reg_layout = swrm_v1_3_reg_layout,
247 .reg_layout = swrm_v1_3_reg_layout,
255 .reg_layout = swrm_v1_3_reg_layout,
275 .reg_layout = swrm_v2_0_reg_layout,
514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], in qcom_swrm_cmd_fifo_rd_cmd()
714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
[all …]
/linux/drivers/tty/serial/8250/
A D8250_dfl.c55 u64 fifo_len, clk_freq, reg_layout; in dfl_uart_get_params() local
86 ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, &reg_layout); in dfl_uart_get_params()
90 uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); in dfl_uart_get_params()
91 reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); in dfl_uart_get_params()
/linux/drivers/dma/
A Dhisi_dma.c164 enum hisi_dma_reg_layout reg_layout; member
369 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_mask_irq()
385 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_unmask_irq()
638 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) { in hisi_dma_init_hw_qp()
803 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_set_mode()
851 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs()
862 if (hdma_dev->reg_layout == HISI_DMA_REG_LAYOUT_HIP08) in hisi_dma_get_ch_regs()
952 enum hisi_dma_reg_layout reg_layout; in hisi_dma_probe() local
960 reg_layout = hisi_dma_get_reg_layout(pdev); in hisi_dma_probe()
961 if (reg_layout == HISI_DMA_REG_LAYOUT_INVALID) { in hisi_dma_probe()
[all …]
/linux/drivers/clk/renesas/
A Drenesas-cpg-mssr.c155 enum clk_reg_layout reg_layout; member
211 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mstp_clock_endisable()
233 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_endisable()
261 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mstp_clock_is_enabled()
300 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_clk_src_twocell_get()
903 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ? in cpg_mssr_suspend_noirq()
934 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_resume_noirq()
943 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) { in cpg_mssr_resume_noirq()
1031 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) in cpg_mssr_reserved_init()
1081 priv->reg_layout = info->reg_layout; in cpg_mssr_common_init()
[all …]
A Drenesas-cpg-mssr.h136 enum clk_reg_layout reg_layout; member
A Dr7s9210-cpg-mssr.c217 .reg_layout = CLK_REG_LAYOUT_RZ_A,
A Dr8a779f0-cpg-mssr.c237 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
A Dr8a779a0-cpg-mssr.c305 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
A Dr8a779g0-cpg-mssr.c304 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
A Dr8a779h0-cpg-mssr.c301 .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
/linux/sound/soc/codecs/
A Dlpass-wsa-macro.c403 const struct wsa_reg_layout *reg_layout; member
1181 wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1183 wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1185 wsa->reg_layout->rx_intx_1_mix_inp2_sel_mask); in wsa_macro_set_prim_interpolator_rate()
1226 wsa->reg_layout->rx_intx_2_sel_mask); in wsa_macro_set_mix_interpolator_rate()
1609 (comp * wsa->reg_layout->compander1_reg_offset); in wsa_macro_config_compander()
1656 (path * wsa->reg_layout->softclip1_reg_offset); in wsa_macro_enable_softclip_clk()
1734 wsa->reg_layout->rx_intx_1_mix_inp0_sel_mask); in wsa_macro_adie_lb()
1740 wsa->reg_layout->rx_intx_1_mix_inp1_sel_mask); in wsa_macro_adie_lb()
2776 wsa->reg_layout = &wsa_codec_v2_1; in wsa_macro_probe()
[all …]
/linux/drivers/clk/samsung/
A Dclk.h293 enum exynos_cpuclk_layout reg_layout; member
305 .reg_layout = _layout, \
A Dclk-cpu.c679 cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout]; in exynos_register_cpu_clock()

Completed in 44 milliseconds