| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| A D | dmub_reg.h | 37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
47 #define FN(reg_name, field) FD(reg_name##__##field) argument
62 REG_SET_N(reg_name, 1, initial_val, \
63 FN(reg_name, field), val)
85 #define REG_UPDATE_N(reg_name, n, ...)\ argument
89 REG_UPDATE_N(reg_name, 1, \
90 FN(reg_name, field), val)
111 #define REG_GET(reg_name, field, val) \ argument
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | reg_helper.h | 56 REG(reg_name), \
61 FD(reg_name##__##field)
163 FN(reg_name, f2), v2)
169 FN(reg_name, f3), v3)
176 FN(reg_name, f4), v4)
184 FN(reg_name, f5), v5)
193 FN(reg_name, f6), v6)
203 FN(reg_name, f7), v7)
214 FN(reg_name, f8), v8)
220 REG(reg_name), FN(reg_name, field), val,\
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| /linux/tools/perf/util/ |
| A D | perf_regs.c | 35 const char *reg_name = NULL; in perf_reg_name() local
38 reg_name = __perf_reg_name_csky(id); in perf_reg_name()
40 reg_name = __perf_reg_name_loongarch(id); in perf_reg_name()
42 reg_name = __perf_reg_name_mips(id); in perf_reg_name()
44 reg_name = __perf_reg_name_powerpc(id); in perf_reg_name()
46 reg_name = __perf_reg_name_riscv(id); in perf_reg_name()
48 reg_name = __perf_reg_name_s390(id); in perf_reg_name()
50 reg_name = __perf_reg_name_x86(id); in perf_reg_name()
52 reg_name = __perf_reg_name_arm(id); in perf_reg_name()
54 reg_name = __perf_reg_name_arm64(id); in perf_reg_name()
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| A D | hw_factory_dcn21.c | 57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 #define REGI(reg_name, block, id)\ argument
65 mm ## block ## id ## _ ## reg_name
67 #define SF(reg_name, field_name, post_fix)\ argument
68 .field_name = reg_name ## __ ## field_name ## post_fix
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
100 .field_name = reg_name ## __ ## field_name ## post_fix
139 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| A D | hw_factory_dce120.c | 46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
60 #define REG(reg_name)\ argument
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| A D | hw_factory_dcn20.c | 59 #define REG(reg_name)\ argument
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
65 #define REGI(reg_name, block, id)\ argument
67 mm ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
103 .field_name = reg_name ## __ ## field_name ## post_fix
158 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| A D | hw_factory_dcn30.c | 66 #define REG(reg_name)\ argument
67 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
69 #define SF_HPD(reg_name, field_name, post_fix)\ argument
72 #define REGI(reg_name, block, id)\ argument
74 mm ## block ## id ## _ ## reg_name
76 #define SF(reg_name, field_name, post_fix)\ argument
77 .field_name = reg_name ## __ ## field_name ## post_fix
109 #define SF_DDC(reg_name, field_name, post_fix)\ argument
110 .field_name = reg_name ## __ ## field_name ## post_fix
165 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| A D | hw_factory_dcn315.c | 63 #define REG(reg_name)\ argument
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 #define SF_HPD(reg_name, field_name, post_fix)\ argument
69 #define REGI(reg_name, block, id)\ argument
71 reg ## block ## id ## _ ## reg_name
73 #define SF(reg_name, field_name, post_fix)\ argument
74 .field_name = reg_name ## __ ## field_name ## post_fix
105 #define SF_DDC(reg_name, field_name, post_fix)\ argument
106 .field_name = reg_name ## __ ## field_name ## post_fix
157 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| A D | hw_factory_dcn32.c | 59 #define REG(reg_name)\ argument
60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
65 #define REGI(reg_name, block, id)\ argument
67 reg ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
101 #define SF_DDC(reg_name, field_name, post_fix)\ argument
102 .field_name = reg_name ## __ ## field_name ## post_fix
169 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/ |
| A D | hw_factory_dcn401.c | 39 #define REG(reg_name)\ argument
40 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
45 #define REGI(reg_name, block, id)\ argument
47 reg ## block ## id ## _ ## reg_name
49 #define SF(reg_name, field_name, post_fix)\ argument
50 .field_name = reg_name ## __ ## field_name ## post_fix
81 #define SF_DDC(reg_name, field_name, post_fix)\ argument
82 .field_name = reg_name ## __ ## field_name ## post_fix
161 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dm_services.h | 96 #define get_reg_field_value(reg_value, reg_name, reg_field)\ argument
99 reg_name ## __ ## reg_field ## _MASK,\
100 reg_name ## __ ## reg_field ## __SHIFT)
112 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ argument
116 reg_name ## __ ## reg_field ## _MASK,\
117 reg_name ## __ ## reg_field ## __SHIFT)
158 …generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name +…
161 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
162 …generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + ins…
168 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| A D | hw_factory_dcn10.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define REGI(reg_name, block, id)\ argument
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
62 mm ## block ## id ## _ ## reg_name
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_panel_cntl.h | 32 #define DCE_PANEL_CNTL_SR(reg_name, block)\ argument
33 .reg_name = mm ## block ## _ ## reg_name
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\ argument
46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## _ ## reg_name
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
60 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| A D | dcn321_resource.c | 117 #define SR(reg_name)\ argument
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
119 reg ## reg_name
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
122 reg ## reg_name
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
147 reg ## reg_name
149 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
150 reg ## reg_name
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| A D | dcn401_resource.c | 102 #define SR(reg_name)\ argument
103 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
104 reg ## reg_name
106 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
107 reg ## reg_name
126 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
137 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
138 reg ## reg_name
140 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
141 reg ## reg_name
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| A D | hw_factory_dce110.c | 42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define REG(reg_name)\ argument
46 mm ## reg_name
48 #define REGI(reg_name, block, id)\ argument
49 mm ## block ## id ## _ ## reg_name
79 #define SF_DDC(reg_name, field_name, post_fix)\ argument
80 .field_name = reg_name ## __ ## field_name ## post_fix
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| A D | dcn35_resource.c | 131 #define SR(reg_name)\ argument
132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
133 reg ## reg_name
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
162 reg ## reg_name
165 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
166 reg ## reg_name
206 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| A D | dcn351_resource.c | 111 #define SR(reg_name)\ argument
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
113 reg ## reg_name
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
142 reg ## reg_name
145 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
146 reg ## reg_name
186 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| A D | dcn301_resource.c | 116 #define SR(reg_name)\ argument
117 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
118 mm ## reg_name
121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
125 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
126 mm ## reg_name
133 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
168 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
179 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
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| /linux/tools/testing/selftests/kvm/aarch64/ |
| A D | debug-exceptions.c | 40 #define GEN_DEBUG_WRITE_REG(reg_name) \ argument
45 write_sysreg(val, reg_name##0_el1); \
48 write_sysreg(val, reg_name##1_el1); \
51 write_sysreg(val, reg_name##2_el1); \
54 write_sysreg(val, reg_name##3_el1); \
57 write_sysreg(val, reg_name##4_el1); \
60 write_sysreg(val, reg_name##5_el1); \
63 write_sysreg(val, reg_name##6_el1); \
66 write_sysreg(val, reg_name##7_el1); \
69 write_sysreg(val, reg_name##8_el1); \
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| /linux/tools/lib/bpf/ |
| A D | usdt.c | 1284 char reg_name[16]; in parse_usdt_arg() local
1292 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1300 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1309 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1385 char reg_name[16]; in parse_usdt_arg() local
1393 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1401 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1414 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1479 char reg_name[16]; in parse_usdt_arg() local
1487 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_dwb.h | 34 #define SR(reg_name)\ argument
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
36 mm ## reg_name
38 #define SRI(reg_name, block, id)\ argument
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
40 mm ## block ## id ## _ ## reg_name
43 #define SRII(reg_name, block, id)\ argument
44 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## id ## _ ## reg_name
47 #define SF(reg_name, field_name, post_fix)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| A D | dcn201_resource.c | 251 #define SR(reg_name)\ argument
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
253 mm ## reg_name
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
264 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
268 .reg_name = ix ## block ## id ## _ ## reg_name
275 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
286 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
287 mm ## reg_name
297 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| A D | dcn32_resource.c | 116 #define SR(reg_name)\ argument
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
118 reg ## reg_name
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
134 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
145 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
146 reg ## reg_name
148 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
149 reg ## reg_name
189 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| A D | dcn302_resource.c | 167 #define NBIO_SR(reg_name)\ argument
168 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
169 mm ## reg_name
176 #define SR(reg_name)\ argument
177 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
183 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
186 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
189 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
193 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
197 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
[all …]
|