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Searched refs:reg_num (Results 1 – 25 of 163) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c166 #define hpd_int_entry(reg_num)\ argument
168 IRQ_REG_ENTRY(HPD, reg_num,\
175 #define hpd_rx_int_entry(reg_num)\ argument
177 IRQ_REG_ENTRY(HPD, reg_num,\
183 #define pflip_int_entry(reg_num)\ argument
185 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
193 IRQ_REG_ENTRY(OTG, reg_num,\
204 IRQ_REG_ENTRY(OTG, reg_num,\
211 IRQ_REG_ENTRY(OTG, reg_num,\
219 IRQ_REG_ENTRY(OTG, reg_num,\
[all …]
/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c117 #define hpd_int_entry(reg_num)\ argument
119 IRQ_REG_ENTRY(HPD, reg_num,\
126 #define hpd_rx_int_entry(reg_num)\ argument
128 IRQ_REG_ENTRY(HPD, reg_num,\
134 #define pflip_int_entry(reg_num)\ argument
136 IRQ_REG_ENTRY(DCP, reg_num, \
143 #define vupdate_int_entry(reg_num)\ argument
145 IRQ_REG_ENTRY(CRTC, reg_num,\
151 #define vblank_int_entry(reg_num)\ argument
153 IRQ_REG_ENTRY(CRTC, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c151 #define hpd_int_entry(reg_num)\ argument
153 IRQ_REG_ENTRY(HPD, reg_num,\
160 #define hpd_rx_int_entry(reg_num)\ argument
162 IRQ_REG_ENTRY(HPD, reg_num,\
168 #define pflip_int_entry(reg_num)\ argument
181 IRQ_REG_ENTRY(OTG, reg_num,\
187 #define vblank_int_entry(reg_num)\ argument
189 IRQ_REG_ENTRY(OTG, reg_num,\
195 #define vline0_int_entry(reg_num)\ argument
197 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dce80/
A Dirq_service_dce80.c92 #define hpd_int_entry(reg_num)\ argument
93 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
107 #define hpd_rx_int_entry(reg_num)\ argument
108 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
121 #define pflip_int_entry(reg_num)\ argument
122 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
136 #define vupdate_int_entry(reg_num)\ argument
152 #define vblank_int_entry(reg_num)\ argument
174 #define i2c_int_entry(reg_num) \ argument
177 #define dp_sink_int_entry(reg_num) \ argument
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c208 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
215 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
235 #define hpd_int_entry(reg_num)\ argument
240 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
242 #define hpd_rx_int_entry(reg_num)\ argument
246 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
249 #define pflip_int_entry(reg_num)\ argument
264 #define vblank_int_entry(reg_num)\ argument
270 #define vline0_int_entry(reg_num)\ argument
285 #define i2c_int_entry(reg_num) \ argument
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c187 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
194 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
214 #define hpd_int_entry(reg_num)\ argument
219 REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
221 #define hpd_rx_int_entry(reg_num)\ argument
225 REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\
228 #define pflip_int_entry(reg_num)\ argument
243 #define vblank_int_entry(reg_num)\ argument
249 #define vline0_int_entry(reg_num)\ argument
264 #define i2c_int_entry(reg_num) \ argument
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/
A Dirq_service_dcn10.c214 #define hpd_int_entry(reg_num)\ argument
216 IRQ_REG_ENTRY(HPD, reg_num,\
223 #define hpd_rx_int_entry(reg_num)\ argument
225 IRQ_REG_ENTRY(HPD, reg_num,\
231 #define pflip_int_entry(reg_num)\ argument
233 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
244 IRQ_REG_ENTRY(OTG, reg_num,\
250 #define vblank_int_entry(reg_num)\ argument
252 IRQ_REG_ENTRY(OTG, reg_num,\
260 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/
A Dirq_service_dcn20.c219 #define hpd_int_entry(reg_num)\ argument
221 IRQ_REG_ENTRY(HPD, reg_num,\
228 #define hpd_rx_int_entry(reg_num)\ argument
230 IRQ_REG_ENTRY(HPD, reg_num,\
236 #define pflip_int_entry(reg_num)\ argument
238 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
249 IRQ_REG_ENTRY(OTG, reg_num,\
255 #define vblank_int_entry(reg_num)\ argument
257 IRQ_REG_ENTRY(OTG, reg_num,\
265 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/arch/sparc/kernel/
A Dpcr.c59 WARN_ON_ONCE(reg_num != 0); in direct_pcr_read()
66 WARN_ON_ONCE(reg_num != 0); in direct_pcr_write()
74 WARN_ON_ONCE(reg_num != 0); in direct_pic_read()
81 WARN_ON_ONCE(reg_num != 0); in direct_pic_write()
115 WARN_ON_ONCE(reg_num != 0); in n2_pcr_write()
119 direct_pcr_write(reg_num, val); in n2_pcr_write()
121 direct_pcr_write(reg_num, val); in n2_pcr_write()
148 (void) sun4v_vt_get_perfreg(reg_num, &val); in n4_pcr_read()
155 (void) sun4v_vt_set_perfreg(reg_num, val); in n4_pcr_write()
206 (void) sun4v_t5_set_perfreg(reg_num, val); in n5_pcr_write()
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/linux/drivers/gpu/drm/amd/display/dc/irq/dce60/
A Dirq_service_dce60.c101 #define hpd_int_entry(reg_num)\ argument
102 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
116 #define hpd_rx_int_entry(reg_num)\ argument
117 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
130 #define pflip_int_entry(reg_num)\ argument
131 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
145 #define vupdate_int_entry(reg_num)\ argument
161 #define vblank_int_entry(reg_num)\ argument
182 #define i2c_int_entry(reg_num) \ argument
185 #define dp_sink_int_entry(reg_num) \ argument
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/
A Dirq_service_dcn314.c238 #define hpd_int_entry(reg_num)\ argument
240 IRQ_REG_ENTRY(HPD, reg_num,\
247 #define hpd_rx_int_entry(reg_num)\ argument
249 IRQ_REG_ENTRY(HPD, reg_num,\
255 #define pflip_int_entry(reg_num)\ argument
257 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
268 IRQ_REG_ENTRY(OTG, reg_num,\
274 #define vblank_int_entry(reg_num)\ argument
276 IRQ_REG_ENTRY(OTG, reg_num,\
284 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
A Dirq_service_dcn315.c243 #define hpd_int_entry(reg_num)\ argument
245 IRQ_REG_ENTRY(HPD, reg_num,\
252 #define hpd_rx_int_entry(reg_num)\ argument
254 IRQ_REG_ENTRY(HPD, reg_num,\
260 #define pflip_int_entry(reg_num)\ argument
262 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
273 IRQ_REG_ENTRY(OTG, reg_num,\
279 #define vblank_int_entry(reg_num)\ argument
281 IRQ_REG_ENTRY(OTG, reg_num,\
289 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/
A Dirq_service_dcn401.c217 #define hpd_int_entry(reg_num)\ argument
219 IRQ_REG_ENTRY(HPD, reg_num,\
226 #define hpd_rx_int_entry(reg_num)\ argument
228 IRQ_REG_ENTRY(HPD, reg_num,\
234 #define pflip_int_entry(reg_num)\ argument
236 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
247 IRQ_REG_ENTRY(OTG, reg_num,\
253 #define vblank_int_entry(reg_num)\ argument
255 IRQ_REG_ENTRY(OTG, reg_num,\
262 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c241 #define hpd_int_entry(reg_num)\ argument
243 IRQ_REG_ENTRY(HPD, reg_num,\
250 #define hpd_rx_int_entry(reg_num)\ argument
252 IRQ_REG_ENTRY(HPD, reg_num,\
258 #define pflip_int_entry(reg_num)\ argument
260 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
271 IRQ_REG_ENTRY(OTG, reg_num,\
277 #define vblank_int_entry(reg_num)\ argument
279 IRQ_REG_ENTRY(OTG, reg_num,\
287 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c248 #define hpd_int_entry(reg_num)\ argument
250 IRQ_REG_ENTRY(HPD, reg_num,\
257 #define hpd_rx_int_entry(reg_num)\ argument
259 IRQ_REG_ENTRY(HPD, reg_num,\
265 #define pflip_int_entry(reg_num)\ argument
267 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
278 IRQ_REG_ENTRY(OTG, reg_num,\
284 #define vblank_int_entry(reg_num)\ argument
286 IRQ_REG_ENTRY(OTG, reg_num,\
301 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c227 #define hpd_int_entry(reg_num)\ argument
229 IRQ_REG_ENTRY(HPD, reg_num,\
236 #define hpd_rx_int_entry(reg_num)\ argument
238 IRQ_REG_ENTRY(HPD, reg_num,\
244 #define pflip_int_entry(reg_num)\ argument
257 IRQ_REG_ENTRY(OTG, reg_num,\
263 #define vblank_int_entry(reg_num)\ argument
265 IRQ_REG_ENTRY(OTG, reg_num,\
271 #define vline0_int_entry(reg_num)\ argument
273 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c236 #define hpd_int_entry(reg_num)\ argument
238 IRQ_REG_ENTRY(HPD, reg_num,\
245 #define hpd_rx_int_entry(reg_num)\ argument
247 IRQ_REG_ENTRY(HPD, reg_num,\
253 #define pflip_int_entry(reg_num)\ argument
255 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
266 IRQ_REG_ENTRY(OTG, reg_num,\
272 #define vblank_int_entry(reg_num)\ argument
274 IRQ_REG_ENTRY(OTG, reg_num,\
282 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/
A Dirq_service_dcn32.c237 #define hpd_int_entry(reg_num)\ argument
239 IRQ_REG_ENTRY(HPD, reg_num,\
246 #define hpd_rx_int_entry(reg_num)\ argument
248 IRQ_REG_ENTRY(HPD, reg_num,\
254 #define pflip_int_entry(reg_num)\ argument
256 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
267 IRQ_REG_ENTRY(OTG, reg_num,\
273 #define vblank_int_entry(reg_num)\ argument
275 IRQ_REG_ENTRY(OTG, reg_num,\
283 IRQ_REG_ENTRY(OTG, reg_num,\
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/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/
A Dirq_service_dce110.c89 #define hpd_int_entry(reg_num)\ argument
90 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
104 #define hpd_rx_int_entry(reg_num)\ argument
105 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
117 #define pflip_int_entry(reg_num)\ argument
118 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
132 #define vupdate_int_entry(reg_num)\ argument
148 #define vblank_int_entry(reg_num)\ argument
170 #define i2c_int_entry(reg_num) \ argument
173 #define dp_sink_int_entry(reg_num) \ argument
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/linux/arch/riscv/kvm/
A Dvcpu_onereg.c216 switch (reg_num) { in kvm_riscv_vcpu_get_reg_config()
268 switch (reg_num) { in kvm_riscv_vcpu_set_reg_config()
425 unsigned long reg_num, in kvm_riscv_vcpu_general_get_csr() argument
444 unsigned long reg_num, in kvm_riscv_vcpu_general_set_csr() argument
466 unsigned long reg_num, in kvm_riscv_vcpu_smstateen_set_csr() argument
480 unsigned long reg_num, in kvm_riscv_vcpu_smstateen_get_csr() argument
578 unsigned long reg_num, in riscv_vcpu_get_isa_ext_single() argument
599 unsigned long reg_num, in riscv_vcpu_set_isa_ext_single() argument
637 unsigned long reg_num, in riscv_vcpu_get_isa_ext_multi() argument
646 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_get_isa_ext_multi()
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A Dvcpu_fp.c93 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_get_reg_fp()
96 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_get_reg_fp()
97 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
102 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_get_reg_fp()
107 reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { in kvm_riscv_vcpu_get_reg_fp()
110 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp()
138 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_set_reg_fp()
141 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_set_reg_fp()
142 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_set_reg_fp()
147 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_set_reg_fp()
[all …]
A Dvcpu_sbi.c175 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_single() argument
184 sext = riscv_vcpu_get_sbi_ext(vcpu, reg_num); in riscv_vcpu_set_sbi_ext_single()
196 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_single() argument
213 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_multi() argument
222 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_set_sbi_ext_multi()
233 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_multi() argument
242 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_get_sbi_ext_multi()
272 reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK; in kvm_riscv_vcpu_set_reg_sbi_ext()
306 reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK; in kvm_riscv_vcpu_get_reg_sbi_ext()
348 reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK; in kvm_riscv_vcpu_set_reg_sbi()
[all …]
A Dvcpu_vector.c96 unsigned long reg_num, in kvm_riscv_vcpu_vreg_addr() argument
103 if (reg_num < KVM_REG_RISCV_VECTOR_REG(0)) { in kvm_riscv_vcpu_vreg_addr()
106 switch (reg_num) { in kvm_riscv_vcpu_vreg_addr()
126 } else if (reg_num <= KVM_REG_RISCV_VECTOR_REG(31)) { in kvm_riscv_vcpu_vreg_addr()
130 (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; in kvm_riscv_vcpu_vreg_addr()
144 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_vector() local
154 rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr); in kvm_riscv_vcpu_get_reg_vector()
170 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_vector() local
180 if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) { in kvm_riscv_vcpu_set_reg_vector()
192 rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr); in kvm_riscv_vcpu_set_reg_vector()
/linux/drivers/video/fbdev/via/
A Dhw.h355 int reg_num; member
361 int reg_num; member
367 int reg_num; member
373 int reg_num; member
379 int reg_num; member
385 int reg_num; member
391 int reg_num; member
397 int reg_num; member
403 int reg_num; member
409 int reg_num; member
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/linux/drivers/irqchip/
A Dirq-imx-irqsteer.c35 int reg_num; member
45 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index()
56 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
146 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler()
150 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler()
196 data->reg_num = irqs_num / 32; in imx_irqsteer_probe()
200 sizeof(u32) * data->reg_num, in imx_irqsteer_probe()
271 for (i = 0; i < data->reg_num; i++) in imx_irqsteer_save_regs()
273 CHANMASK(i, data->reg_num)); in imx_irqsteer_save_regs()
281 for (i = 0; i < data->reg_num; i++) in imx_irqsteer_restore_regs()
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