Searched refs:req_dppclk (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn21/ |
| A D | dcn21_dccg.c | 46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
55 if (req_dppclk) { in dccg21_update_dpp_dto()
67 phase = (req_dppclk + 9999) / 10000; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| A D | dcn20_dccg.c | 47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
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| A D | dcn20_dccg.h | 438 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| A D | dcn31_dccg.c | 46 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg31_update_dpp_dto() argument
58 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
64 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg31_update_dpp_dto()
80 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg31_update_dpp_dto()
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| A D | dcn31_dccg.h | 206 int req_dppclk);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn201/ |
| A D | dcn201_dccg.c | 48 int req_dppclk) in dccg201_update_dpp_dto() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| A D | dcn401_dccg.c | 77 void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg401_update_dpp_dto() argument
81 if (dccg->ref_dppclk && req_dppclk) { in dccg401_update_dpp_dto()
87 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg401_update_dpp_dto()
102 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg401_update_dpp_dto()
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| A D | dcn401_dccg.h | 195 void dccg401_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| A D | dcn35_dccg.c | 1143 int req_dppclk) in dccg35_update_dpp_dto() argument
1154 if (dccg->ref_dppclk && req_dppclk) { in dccg35_update_dpp_dto()
1160 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg35_update_dpp_dto()
1174 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg35_update_dpp_dto()
2104 int req_dppclk) in dccg35_update_dpp_dto_cb() argument
2115 if (dccg->ref_dppclk && req_dppclk) { in dccg35_update_dpp_dto_cb()
2121 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg35_update_dpp_dto_cb()
2138 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg35_update_dpp_dto_cb()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dccg.h | 98 int req_dppclk);
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